GATE CSE 2016 | Set 2 | Question: 33

Question

Consider a $3 \ \text{GHz}$ (gigahertz) processor with a three stage pipeline and stage latencies $\large\tau_1,\tau_2$ and $\large\tau_3$ such that $\large\tau_1 =\dfrac{3 \tau_2}{4}=2\tau_3$. If the longest pipeline stage is split into two pipeline stages of equal latency , the new frequency is __________ $\text{GHz}$, ignoring delays in the pipeline registers.

Comments

INTRESTING

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ANS : 4Ghz

 

 

 

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To know which is larger , let's say t1 = 3/4 t2 = 2 t3 = k
then t1 = k , t2 = 4/3 k , t3 = 1/2 k.
now all are in same ratio , then latencies k : 4/3 k : 1/2 k
larger is 4/3 k which is equal to cycle time 1/3 ns , then k = 1/4 ns means 4 GHz.
splitting 4/3 k into 2 latencies -> 2/3 k , 2/3k
new stage pipeline system have latencies k , 2/3 k , 2/3 k , 1/2 k.
larger is k , so we know k is 4 GHz

Answer 1

Answer is 4 GHz.

Given $3$ stage pipeline , with $3\text{ GHz}$ processor.

Given , $e_1 =\dfrac{3e_2}{4}=2e_3$

Put $e_1 = 6x$ 

  we get, $e_2 = 8x\  , e_3 = 3x$

Now largest stage time is $8x$.

So, frequency is $\dfrac{1}{8x}$

$\Rightarrow\dfrac{1}{8x}=3 \text{GHz}$  

$\Rightarrow\dfrac{1}{x}=24\text{ GHz}\quad \rightarrow (1)$

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Now, we divide $e_2$  into two stages  of $4x\ \&\ 4x.$

New processor has $4$ stages -

$6x,\ 4x,\ 4x,\ 3x.$

Now largest stage time is $6x$.

So, new frequency is 

$\dfrac{1}{6x}$ = $\dfrac{24}{6}$ =  4 GHz (Ans)  $[\because \text{from}\; (1)]$ 

Comments

Ans

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@S_Sandeep These Types of Questions are not purely COA but involves mix of aptitude and maths . Watch Vishvadeep sir PYQ playlist on YT , he has done these all Questions and explained the way he did in his paid classes . 

 

 

Playlist Link : Playlist

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statement “clock frequency is fixed and intrinsic to the processor” is correct — but here “processor” before and after splitting are two different processor designs

Answer 2

Answered by Vishvadeep Gothi sir on GateWallah Youtube channel!!

Comments

thanks bro

Answer 3

I hope this way it's more easy to understand

 

 

Comments

Very useful and understand easily

Answer 4

Consider, for first case t1=k, t2=4k/3, t3=k/2

Now, for n instructions time to complete the execution is with $3 * 10^9$ Hz clock speed is $n * (1/3) * 10 ^{-9} (\because CPI = 1 $ for pipelined processors).

According to 3-stage pipeline time for n instructions would be :${k}+{4k/3}+{k/2}+{{(n-1)} *{4k/3}}$

by equating these two

$n * (1/3) * 10 ^{-9} {=} {k}+{4k/3}+{k/2}+{{(n-1)} *{4k/3}} $

$ \therefore  (1/3) * 10 ^{-9} {=} {k/n}+{k/2n}+{4k/3} $

So if n is very large we can do,

 $ \lim _ {n \to \infty  } \left ( (1/3) * 10 ^{-9} {=} {k/n}+{k/2n}+{4k/3} \right ) $

By solving this,

$ (1/4) * 10 ^{-9} {=} {k}$

 

Now, we divide 2nd stage so t1=k, t2=2k/3,t3=2k/3, t4=k/2

Consider x to be the resultant frequency or clock speed.

By following the exact same procedure as above, Taking longest pipeline stage as stage 1.

${1/x} {=} {k}$

$ \therefore x {=} {1/k}$

$\therefore x {=} {4 * 10^{9}}$

which is 4 GHz.

Comments

The eqn. should be (n + 2 ) * (4k / 3 )  instead of

(n + 2 ) * (4k / 3 ) = n / (3 * 10^9 )  

Then for n -> inf.

k = (1 / 4 ) * 10^-9

now for 4 - stage since k is large

we get 4GHz.

Answer 5

here frequency=3GHZ 

cycle time =1/frequency=1/3 *10^-9 sec

here pipeline has 3 stages and stage delay is given as : 

τ₁  = 3/4τ₂ = 2τ₃ 

now equate all stage delay in terms of τ_1, so that we can distinguish the largest delay _.

and that is :τ₁  = 4/3 τ₁ = 1/2 τ₁

so here we got  4/3 τ₁ is the largest delay_.(  number of input is not given so we are assuming it would be a very lage number .)

time taken by pipeline is : (K+n-1)cycle time ,  where( cycle time = largest stage delay+buffer delay + some extra overhead ) and we have only stage delay so cycle time will be that only .now we can write it as :

n*4/3 τ_{1  =}  n* 3*10^-9  ( n is very large so rest calculation with it will be negligible )

and here we got , τ₁ =1/4 * 10^-9 ,

split the  largst stage in two stages with equal delay :

stage1= τ₁ ,stage 2= 4/6 τ_{1 stage 3 =} 4/6 τ_{1 ,} stage4 ₌  τ_1/2  

and  the largest delay = cycle time is now τ1  which is 1/4 *10^9

so frequency = 4GHZ

Answer 6

 

We can also find the t1, t2 and t3 and then find the new stages and their cycle time and then finally new frequency.