I-Cache and D-cache

Question

consider a system with CPI of 1.2 cycles assuming memory access always results in cache hit. Processor run at 2 GHz. Consider a program running on this system has 30% Load and store instructions. The processor has an I-cache with miss rate of 2% and a D-cache with miss rate of 5%. The hit time is 1 clock cycle. The miss penalty for both the cache is 50 ns.
What is the overall CPI including both instruction and data access?_______

Comments

assuming memory access always results in cache hit

processor has an I-cache with miss rate of 2% and a D-cache with miss rate of 5%

How can these 2 statements be true simultaneously?

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Oh right ...Thanks for pointing out this.

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Yeah, but which one to assume correct then?

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I think we shoul not consider that statement always hit...
Then what should the process to solve this like we should to find miss penality for I cache then D cache in terms of Cycles then overall sum. is it right approach or what should be?

 

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what is the answer?