8 stage ripple counter means 8 bit standard asynchronous counter by which we mean that :
a) The clock input is supplied to flip flop corresponding to LSB.
b) The clock input of ith flip flop is supplied by the output of (i-1) th flip flop.
Thus if we consider these two points we have to take into account that every flip flop will contribute to the operation of clock.So in other words for proper operation of ripple counter , the clock frequency should be inverse of n*tpd i.e.
Clock frequency = 1 /( n * tpd ) where n is the number of flip flops and tpd is the propogation delay of 1 flip flop.
But in addition to that we know that after applying clock pulse and going through each of the flip flops we have decoder to show output of the counter .But the problem comes when it is transiting to 0 , it may be possible to transit through intermediate states thus producing the decoding error which is commonly known as glitch.
Hence to avoid glitch we apply strobe pulse after the delay introduced by flip flops.
Hence the clock frequency required to drive the ripple counter = 1 / (n*tpd + Ts) where Ts stands for strobe pulse time.
Thus substituting n = 8 , tpd = 75 ns and Ts = 50 ns
Hence clock frequency required = 1 / ((8 * 75 + 50) * 10-9) Hz
= 1.538 MHz