0 votes 0 votes closed with the note: Resolved.... Thanks Arjun sir I am not getting any difference between these two questions but answers are not matching, https://gateoverflow.in/86195/me-test https://gateoverflow.in/26442/gate1991-5-c Digital Logic sequential-circuit digital-circuits digital-logic + – Shaik Masthan asked Jul 29, 2018 • closed Jul 29, 2018 by Shaik Masthan Shaik Masthan 1.4k views comment Share Follow See all 27 Comments See all 27 27 Comments reply Show 24 previous comments Dushyant Raut 4 commented Dec 26, 2018 reply Follow Share @Shaik Masthan In your expalanation you said we are not considering output from third and gate but from third flip flop. But from diagram it is not clear. It seems like they are taking output from final AND gate. pls reply 0 votes 0 votes Shaik Masthan commented Dec 27, 2018 reply Follow Share @Dushyant Raut 4 But from diagram it is not clear. yes, it is not clearly informed where they are taking the o/p. But in general we take o/p at FlipFlop, so answered as per that, If it is specified take the o/p at AND gate then we have to consider 3$^{rd}$ AND gate Delay also :) 1 votes 1 votes PRANAVCOOL commented Oct 30, 2020 i edited by PRANAVCOOL Oct 30, 2020 reply Follow Share sir, can you please tell what definition to follow to calculate the propagation time in synchronous and asynchronous counters, and for time period of cycle i got how ro solve this ques but very confused what is the definition to follow for write ans. 0 votes 0 votes Please log in or register to add a comment.