The Gateway to Computer Science Excellence

0 votes

I am not getting any difference between these two questions but answers are not matching,

https://gateoverflow.in/86195/me-test

closed with the note:
Resolved.... Thanks Arjun sir

0

yes sir.... my approach is matching with other person but not with you...

i read all the comments but i am not getting why you are not consider one more delay by and AND gate.

your comments on that question i am not getting

thats the same delay rt?

suppose the circuit was not the same, we should have considered all these stages, and taken the maximum time period (min. frequency).

Because answers are given by different people :)

then one of the answer should be wrong, right?

0

@Shaik

Is it need to consider each AND gate delay, when clock is operated one time?

They have not mentioned, that considering every AND gate

each Flip flop get clock pulse at the same time

right?

0

See in synchronous counter, we get output for last FF right?

Now See diagram

So, it is taking value of last two AND gate (1 for propagation delay of JK and other one last AND)

i.e. why it is 10+10=20

right?

I think that 10 is propagation delay of FF

0

No... your approach is wrong...

For the output the last AND gate ( After the third FF) is never required.... why because we are taking output at Q0 of last Flip-Flop.

My Doubt is Why Arjun sir didn't consider the delay of AND gate (which is between First FF and Second FF), Sir only consider only the delay of AND gate (which is between Third FF and Second FF),

Note that My Third FF is generating the output

For the output the last AND gate ( After the third FF) is never required.... why because we are taking output at Q0 of last Flip-Flop.

My Doubt is Why Arjun sir didn't consider the delay of AND gate (which is between First FF and Second FF), Sir only consider only the delay of AND gate (which is between Third FF and Second FF),

Note that My Third FF is generating the output

0

but Sir formula for

Synchronous circuit is=$\frac{1}{t_{pd}}$

And for Asynchronous circuit=$\frac{1}{n\times t_{pd}}$

then why do we need to consider $t_{pd}$ of every FF?

Synchronous circuit is=$\frac{1}{t_{pd}}$

And for Asynchronous circuit=$\frac{1}{n\times t_{pd}}$

then why do we need to consider $t_{pd}$ of every FF?

0

Sir, your answer is

Time to get output from FF=10 ns.

Time for inputs to reach FF2=10. (One AND gate)

Time for inputs to reach FF3=20. (Two AND gates)

So, minimum time period needed for clock is 10+max(0,10,20)=10+20=30 ns

10+max(0,10,20)

what is this 10 ? is it FF propagation delay ?

if yes, remove the line

Time to get output from FF1=10 ns.

due to it create confusion, and add the line

Time for inputs to reach FF1=0. ( Zero AND gate )

0

yes, sir.... Thank you so much for sparing time for me.

sir we can't privately message you due to you disabled it...

In the HOME page, **Question** of the day typed mistakenly

+1

Oh. Will be removing Question of the Day soon as most questions remaining are not relevant. Also, will enable Private Messaging for contributing users- currently there is no facility for this.

0

Still getting some confusion

1)why ME question minus 2 has been done?

If logic is All AND gate delay other than last AND gate has been taken, then in ME question, it should be minus 1?

2) Why last AND gate delay not taking?

1)why ME question minus 2 has been done?

If logic is All AND gate delay other than last AND gate has been taken, then in ME question, it should be minus 1?

2) Why last AND gate delay not taking?

+1

Why last AND gate delay not taking?

we are not taking output at AND gate, we are taking output at Third FlipFlop,

why ME question minus 2 has been done?

in ME question, there is no AND gate Between first Flip Flop and Second Flip Flop.

and More over he is comparing **AND gates** with no.of flip flops., i.e., First Flip flop and Last Flip Flop doesn't have AND gates

+2

@Srestha mam,

Frequency of Synchronous circuit is=$\frac{1}{T_{pd}}$

Frequency of Asynchronous circuit=$\frac{1}{n*T_{pd}}$

These Formulas are true when There are no AND gates between the Flip-Flops. ( Formulas are changing depend upon the situation )

why do we need to consider T

_{pd}of every FF?

Here we didn't consider Tpd for Every Flip Flop, Here considering each AND gate ( due to AND gates connected in Series. )

+1

Yes. No use in knowing that formula because in GATE they can add any different combinational circuit between the FFs.

0

@Shaik @Arjun Sir

why propagation delay 10 taking separately

I mean $max\left ( 0,10,20 \right )$ , it is already counting propagation delay of each FF

then why ${\color{Red} {10}}+max\left ( 0,10,20 \right )$

that 1st 10ns delay is needed?

why propagation delay 10 taking separately

I mean $max\left ( 0,10,20 \right )$ , it is already counting propagation delay of each FF

then why ${\color{Red} {10}}+max\left ( 0,10,20 \right )$

that 1st 10ns delay is needed?

0

I mean

max(0,10,20) , it is already counting propagation delay of each FF

it is counting, how much time to reach the FF only.

then, FF takes 10 ns to produce the output.

0

In your expalanation you said we are not considering output from third and gate but from third flip flop.

But from diagram it is not clear. It seems like they are taking output from final AND gate.

pls reply

- All categories
- General Aptitude 1.9k
- Engineering Mathematics 7.5k
- Digital Logic 2.9k
- Programming and DS 4.9k
- Algorithms 4.4k
- Theory of Computation 6.2k
- Compiler Design 2.1k
- Databases 4.1k
- CO and Architecture 3.4k
- Computer Networks 4.2k
- Non GATE 1.4k
- Others 1.4k
- Admissions 595
- Exam Queries 573
- Tier 1 Placement Questions 23
- Job Queries 72
- Projects 18

50,737 questions

57,342 answers

198,451 comments

105,214 users