Split Phase | Self-Doubt | COA

Question

How is split phase implemented in the hardware?

For common register access between two stages, how is one clock cycle (Giving half a clock cycle to each of the stages) enough to satisfy work for both stages?

Any reference to standard resources will also help.

Comments

I’ll go through it.

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@DebSujit it is basically implementing parallel instruction execution through pipelining + multithreading. I couldn’t quite process the technicalities to a good depth from the book but I found an article which explains the concept fairly simply, still this implementation pose challenges regarding data inconsistency.

@DebSujit Thanks a lot for the reply.

Article Link: What is superscalar architecture? (iu.edu)

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@Sunnidhya Roy Great. Thanks for replying too.