Split Phase | Self-Doubt | COA

Question

How is split phase implemented in the hardware?

For common register access between two stages, how is one clock cycle (Giving half a clock cycle to each of the stages) enough to satisfy work for both stages?

Any reference to standard resources will also help.

Comments

@DebSujit each phase of the pipeline is further broken down into multiple micro instructions which requires different control signals right? These micro-instructions gets only 1 clock cycle to execute if we consider RISC architecture(each phase of pipeline requires 1 cycle to execute).

Now suppose current instruction wants to write the contents of the ALU’s local registers(T,S) to the GPRS and the next instruction also wants to read the contents of the GPRS set, so these operations can be accomplished by nothing but micro instructions right? As RISC uses hardwired CU necessary control signals will be made active based on the time divisions say 1 clock cycle is divided into T1 T2 subphases, the micro instructions to write the contents of the ALU registers(T,S) will be done in the T1 phase and the micro instructions to read the updated value of the GPRS is done in the T2 phase thus enabling common register access between 2 stages.

You can refer to different types of implementation of Control Unit in Morris Mano.

 

---

@Sunnidhya Roy

If that is the case and one clock cycle is sufficient to perform two stages of different instruction, why only use it in need of data forwarding? Why can't be it any two stage? 

Can we perform ID stage of two different instruction in same clock cycle by split phasing which are reading from two different registers?

If yes, then why don't we use it often.? 

---

@DebSujit

I guess it can cause data inconsistency. 

For instance I have two instructions like these:

1. Load R1,(R2)
2. JNZ DestinationNode

In this case suppose ID stage of both instructions are executed together and suppose initial value of R1 is 10 but after completion of 1^st instruction it would become 0, however JNZ instruction in the meantime gets executed based on the older value and jumps to the destination node even though it was not supposed to.

So I am thinking that to avoid these kind of challenges split cycle is preferred mostly in data forwarding scenarios or some other scenarios where such kind of data inconsistency might not arise.

I hope you got it.

---

@Sunnidhya Roy

Yes, that is what I’m saying I have seen very few questions actually using split phase when there are two completely independent instructions and they are not optimized using split phasing.

For instance,

1. $R_1←R_1+R_2$

2. $R_3←R_2+R_3$

Can we complete the ID stage of both these processes in a single cycle using split phase as there’s no data dependency? Apart from that, there is some structural dependency as R2 is accessed in both but we can overcome that using split phasing.

---

@DebSujit

For the given Instructions I suppose Split phasing can work as there is no data dependency but I am not sure what the standard procedure is, Ideally speaking nowadays most of the setups support data forwarding through intermediate buffers/latches and certain code optimization techniques, thus almost completely removing data dependency. 

We need some confirmations I guess from somebody experienced as I am not able to find any suitable articles regarding the implementation. 

@DebSujit if you know somebody from Gate Overflow who can clarify this confusion can you please tag them?

---

I have mailed some professors from renowned institutions. I’ll wait for their reply.

---

@DebSujit Thanks a lot, do let me know if you get any reply.

---

I’ll go through it.

---

@DebSujit it is basically implementing parallel instruction execution through pipelining + multithreading. I couldn’t quite process the technicalities to a good depth from the book but I found an article which explains the concept fairly simply, still this implementation pose challenges regarding data inconsistency.

@DebSujit Thanks a lot for the reply.

Article Link: What is superscalar architecture? (iu.edu)

---

@Sunnidhya Roy Great. Thanks for replying too.