edited by
3,252 views
8 votes
8 votes

Consider a small $2$-way set-associative cache memory, consisting of four blocks. For choosing the block to be replaced, use the least recently (LRU) scheme. The number of cache misses for the following sequence of block addresses is $8, 12, 0, 12, 8$

  1. $2$
  2. $3$
  3. $4$
  4. $5$
edited by

2 Answers

Best answer
8 votes
8 votes

We have 4 blocks and 2 blocks in a set . there are 2 sets.

 

since the lowest bit of block address is used for indexing into the set. 

So, 8, 12 and 0 first miss in cache with 0 replacing 8 and then 12 will be hit in cache and 8 again miss. So totally 4 misses. 

selected by
Answer:

Related questions

5.9k
views
4 answers
8 votes
go_editor asked Jun 10, 2016
5,932 views
The principal of the locality of reference justifies the use ofvirtual memoryinterruptsmain memorycache memory
4.9k
views
5 answers
11 votes
go_editor asked Jun 10, 2016
4,941 views
In the Big-Endian system, the computer storesMSB of data in the lowest memory address of data unitLSB of data in the lowest memory address of data unitMSB ... address of data unitLSB of data in the highest memory address of data unit
7.3k
views
2 answers
8 votes
go_editor asked Jun 10, 2016
7,309 views
In comparison with static RAM memory, the dynamic Ram memory haslower bit density and higher power consumptionhigher bit density and higher power ... bit density and lower power consumptionhigher bit density and lower power consumption
4.8k
views
2 answers
6 votes
go_editor asked Jun 10, 2016
4,813 views
A read bit can be readand written by CPUand written by peripheralby peripheral and written by CPUby CPU and written by the peripheral