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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2024-1} & \textbf{2024-2} & \textbf{2023} &  \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 2&2&2& 3 &1&2&1&2&3
\\\hline\textbf{2 Marks Count} & 3&3&4& 2 &2&2&2&2.67&4
\\\hline\textbf{Total Marks} & 8&8&10& 7 &5&6&\bf{5}&\bf{7.33}&\bf{10}\\\hline
\end{array}}}$$

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Most answered questions in CO and Architecture

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3481
Made-easy test-series
Someone please solve the question.
Someone please solve the question.
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2 votes
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3483
Control Unit
How many clock cycle are needed in index addressing for getting memory content and effective address?
How many clock cycle are needed in index addressing for getting memory content and effective address?
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3485
CO Doubt
default strict or hierarchical model used in co in memory hierarchy?
default strict or hierarchical model used in co in memory hierarchy?
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3486
TestSeries
I am really confused, In questions like this, when do we have to use the access time? Is the access time included in writing/updation time here?
I am really confused, In questions like this, when do we have to use the access time? Is the access time included in writing/updation time here?
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3 votes
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3490
Memory Reference count
Consider the 2 GHz clock frequency processor used execute the following program segment. Assume that memory reference consumers 4 cycles and ALU operations consumes 2 cycles then total time required to complete the program execution (in ns) is ___________.
Consider the 2 GHz clock frequency processor used execute the following program segment.Assume that memory reference consumers 4 cycles and ALU operations consumes 2 cycl...
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3491
PipeLine
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3492
CO - BIT MANIPULATION INSTRUCTIONS
What is the purpose of having SHL & SHLA, when both perform the same operations. SHRA is useful in division of numbers in sign magnitude representation by any power of 2. But why is SHLA required?
What is the purpose of having SHL & SHLA, when both perform the same operations. SHRA is useful in division of numbers in sign magnitude representation by any power of 2....
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2 votes
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3494
question
The minimum size of the ROM which maintains truth table of square of 3 bit numbers is __________ (in bits).
The minimum size of the ROM which maintains truth table of square of 3 bit numbers is __________ (in bits).
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1 votes
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3496
gate2005
Is it possible to have vectored interrupt on processors with single interrupt request and grant line?
Is it possible to have vectored interrupt on processors with single interrupt request and grant line?
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1 votes
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3497
pipeLine
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3498
TEST_SERIES
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3499
gate 2005
How is I/O protection ensured by CPU having isolated mapped I/O?
How is I/O protection ensured by CPU having isolated mapped I/O?
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3500
Made Easy CO
Suppose that in 1000 memory references there are 40 misses in L1 and 20 misses in L2 cache. Assume miss penalty from L2 to memory is 100 cycles. The hit time of L2 is 10 clock cycles. The hit time of L1 is 1 clock cycle. What is the average memory access time ?
Suppose that in 1000 memory references there are 40 misses in L1 and 20 misses in L2 cache. Assume miss penalty from L2 to memory is 100 cycles. The hit time of L2 is 10 ...
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