13 votes 13 votes 1. In case of no data forwarding can we use split phase. 2. Should we have to consider data forwarding, According to options? 3. Where we can use split phase??( I know about WB-ID and EX-ID) @Pc @Arjun Sir Please answer.. CO and Architecture co-and-architecture pipelining + – vaishali jhalani asked Jan 30, 2017 • retagged Nov 13, 2017 by Arjun vaishali jhalani 2.4k views answer comment Share Follow See all 17 Comments See all 17 17 Comments reply vaishali jhalani commented Jan 30, 2017 reply Follow Share If any one have doubts other than these 3...add here 0 votes 0 votes Arjun commented Jan 30, 2017 reply Follow Share 1. Yes. They are not related. 2. By default consider it, if not in option do without it. Same applies for any topic any subject - choices are also to be used for decision making. 3. This is not standard answer - but yes, those two must be the only ones in a classical pipeline. 7 votes 7 votes vaishali jhalani commented Jan 30, 2017 reply Follow Share What about split phase in EX-OF? I think it is same as EX-ID 0 votes 0 votes Akriti sood commented Jan 30, 2017 reply Follow Share @arjun sir,can we do EX of next instruction and ID of previous instruction in sam cycle if previous instruction is loading a value to a register and next instruction needs that register for addition in case of no forwarding?? 0 votes 0 votes Akriti sood commented Jan 30, 2017 reply Follow Share also when instruction is like LW R1,#400 in this instruction 400 is an immediate operand,so R1 will be loaded in WB stage or MEM stage?? 0 votes 0 votes vaishali jhalani commented Jan 30, 2017 reply Follow Share WB stage 1 votes 1 votes Dulqar commented Jan 30, 2017 reply Follow Share Load Instruction will be in Memory Stage , right ? 0 votes 0 votes vaishali jhalani commented Jan 30, 2017 reply Follow Share ????? 0 votes 0 votes pC commented Jan 31, 2017 i edited by pC Jan 31, 2017 reply Follow Share @arjun sir , https://web.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/forward.html here they havn't considered split phase by default . Why ? Like in GATE2015 . If Question says that there is Operand Forwarding from stage A to stage B then we should consider split phase A/B ( Though they are not related . This wording in question says in rising clock cycle use stage A the falling edge use satage B) This was my conculusion . is this correct ? There had been so much discussions here 0 votes 0 votes yg92 commented Feb 1, 2017 reply Follow Share @pC / @Arjun Sir / @Sushant / @Debashish Could you please suggest how to identify looking at the question wether to use multiple output stage buffers or not? If options are given it could be guessed but not in Numerical Data. Also, Initially this was my assumption - If there are non-uniform stage delays for instructions we should assume multiple stage output buffers. Is this assumption correct? Below are some of the exactly similar models but none of them have consistency in their solutions. Multiple StageBuffer not assumed - https://gateoverflow.in/56994/pipelining Multiple StageBuffer assumed - https://gateoverflow.in/1314/gate2009-28 Multiple StageBuffer not assumed - https://gateoverflow.in/1512/gate1999_13?show=1512#q1512 2 votes 2 votes Arjun commented Feb 1, 2017 reply Follow Share Multiple stage buffer - use it when there is a use :) That is if it can imporve the no. of cycles required use it unless otherwise stated in question or choice given otherwise. 1 votes 1 votes srestha commented Feb 1, 2017 reply Follow Share Sir , in 3 links posted by @ yashgupta1992 each case we can apply stage buffer. But why we are using stage buffer in case of only in https://gateoverflow.in/1314/gate2009-28 but not others. If we not apply stage buffer in https://gateoverflow.in/1314/gate2009-28 the answer will be different. 1 votes 1 votes Arjun commented Feb 1, 2017 reply Follow Share @srestha As told, you can use anywhere- but it matters only when answer changes. By default most question won't be having stage buffers or it won't change the answer. The 2009 question was different- either the Prof intentionally meant that or he missed that point. Anyway due to the choices there was no ambiguity. Suppose the same question was asked now without choices, I'm sure marks would be given to both the answers (with and without multi stage buffers). But there is only 0.00001% chance of such a question coming now. 5 votes 5 votes Rahul Jain25 commented Feb 1, 2017 reply Follow Share Gate has been ambiguous about pipelining. In 2015 and 2010 pipelines questions different answers are comin than that in answer key. @ Arjun sir, EX-ID split is not applicable by default only WB-ID is taken by default isn't it??? 0 votes 0 votes Arjun commented Feb 1, 2017 reply Follow Share @Rahul When data is ready we can always use split phase access. 1 votes 1 votes Rahul Jain25 commented Feb 1, 2017 reply Follow Share @ Arjun sir in split phase in rising edge one task is completed and falling edge other task in this way we have split phse. It is known we have WB-ID. But how can I identify if data is ready or not in half clock cycle or how can I know if data is ready and I can do split phase??? 0 votes 0 votes Anjana Babu commented Feb 2, 2017 reply Follow Share @Arjun SIR if split-phase is used data is avilable to next instruction in same clock cycle itself . If no split-phase then data will be avilable in next clock cycle only . Is this correct ? 0 votes 0 votes Please log in or register to add a comment.