GATE CSE 1991 | Question: 5-c

Question

Find the maximum clock frequency at which the counter in the figure below can be operated. Assume that the propagation delay through each flip flop and each AND gate is $10\;\text{ns}$. Also, assume that the setup time for the $JK$ inputs of the flip flops is negligible.

Comments

What I know is Total time (Propagation) = T(flip flop) + T(combinational circuit)

So from the above Total time= 10(Flip Flop) + 30(combinational AND gate);

f=1/T and we can solve easily . But here why only one AND gate delay is considered ?

Expalin plz.

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@bikram sir

Answer not should be 30(3 And Gate ) + 10 ( Synch Circuit) = 40 ns

1/40 ns= 25 Mhz ?

Why here they have taken it only for 1 And and 1 FF ?

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This might be silly but I can't see any combinational circuit such that output of flip flops is again given to input of flip flops. plz help.

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Can You check K1, K2?

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[KINDLY IGNORE THE YELLOW PATH WITHIN FF2]

I understood it in this way . I’m adding my answer just in case someone finds it easier to assimilate.

we determine the current state of each FF based on the previous state of FF. 

In the diagram , lets say the current state values are at Aout , Bout and Cout . It will take effect once Ain , Bin and Cin is available from the previous state.

For FF1 to change state (Follow the green path):

 t1 = Time for Ain to generate + time for FF1 to propagate = 0 (it’s always high)+ 10 = 10ns

 

For FF2 to change state (follow the blue path):

t2 = Time to generate Bin + time for FF2 to propagate

    = Time to generate Aout + Time for logic 1 + time for AND gate + time for FF2 to propagate

    = 0(Aout is already there from prev state) + 0(always high) + 10 + 10

    = 20 ns 

 

For FF3 to change state(follow the yellow path):

t3 = Time to generate Cin + time for FF3 to propagate

    = time for Bout + time for Bin + time for AND gate + time for FF3 to propagate

    = 0 + time for Bin + time for AND gate + time for FF3 to propagate (Bout is already there from prev state , hence time is 0)

   =  Time to generate Aout + Time for logic 1 + time for AND gate + time for AND gate + time for FF3 to propagate

   = 0 + 0 + 10 + 10 + 10 (like Bout , Aout is already there from previous state)

   = 30ns

 

So time taken for FF1 , FF2 and FF3 to change their respective states are 10 , 20 and 30 ns . We take the maximum time among it i.e 30 ns as it will ensure that no FF is left out.

 

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The questions is Controversial and ambiguous. Answer could be 30ns OR 40ns, depending on how we interpret the question.

So, DON’T worry and don’t waste time.

See the discussion here :

https://electronics.stackexchange.com/questions/328294/maximum-frequency-of-the-synchronous-counter

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Hi , just gathered from here and there , little analysis from my side . 😀 

Answer 1

In a $\text{JK}$ flip flop the output toggles when both $\text{J}$ and $\text{K}$ inputs are $1.$ So, we must ensure that with each clock the output from the previous stage reaches the current stage.

Setup time is defined as the minimum amount of time before the clock's active edge that the data must be stable for it to be latched correctly

It is given that setup time is negligible - means as soon as data is stable, the next clock can be given. 

• Time to get output from $FF$ once input (and clock) is given  $= 10ns.$ (Propagation Delay)
• Time for inputs to reach $FF_1 = 0.$ (Zero AND gate)
• Time for inputs to reach $FF_2 = 10.$ (One AND gate)
• Time for inputs to reach $FF_3 = 20.$ (Two AND gates)

So, minimum time period needed for clock is $10 + \max(0,10,20) = 10 + 20 = 30ns$ which would mean a maximum clock frequency of $1/30 GHz = 33.33 MHz$

Comments

@mrinmoyh

Let’s say, we are starting the FFs now. They will be in some initial state, eg Q0Q1Q2=000. Now these are outputs from those different FFs which are available and can be used wherever they are needed as inputs. Similarly, at each clock pulse, we will have the previous state value, which we will use to generate the next state (which is basically how FFs work)

We start with the first clock. Let us first calculate the input delays for each FF and nothing else. 

The delay to get inputs available at:-

• J0K0 is 0, which is quite clear.
• J1K1 is 10 ns. Why? Because J1 = 1 AND Q0 (On a different note, you might think this is not a very optimal way of implementation, I agree with that, but here 1 is acting like a switch and we can make 1 as 0 and control the inputs at J1K1, just extra info). So a delay of ! AND is involved
• J2K2 is 20 ns. Why? Because J2 =  (1 AND Q0) AND Q1. So here a delay of 2 AND gates are involved. Note that the inputs to 1^st AND gate are 1, Q0 which are already available (Q0 is the output from previous state and not current state so we don’t have to consider the FF delay for getting Q0), and for 2^nd AND gate Q1 is readily available but it is also using the output of 1^st AND gate, and hence the total delay becomes 20ns for J2K2

So now we have the input delays for each FF as 0ns, 10ns, 20ns. All we have to do is add FF delay, so the total delays would become 10ns, 20ns, 30ns. Maximum is 30 ns and so the minimum time period is 30 ns. 

Giving us a maximum frequency of  = 1/30 GHz

= 33.333333333333333333333333333333333333333333333333333333333 MHz     (:P)

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@Pratyush Priyam Kuan

Your approach is partially correct. here’s why

I think there are two possible approaches:-

1. At the start of clock pulse, only outputs from previous states are available. They will have to go through the combinational circuits, and then the results can be used as inputs for the FFs to calculate the output for current state (which is what i have explained in the above comment)
2. At the start of clock pulse, the outputs from previous states, as well as the required inputs for FFs for current state are also available. So we can immediately calculate the output for current state using those inputs. After that, we will have to use this current state output, feed them to the combinational circuits, and make sure that the inputs are available for the respective FFs before clock ends. These inputs will be used by the FFs in the next clock pulse

From your comment, it seemed that you were trying to use the current state o/p of one FF into another FF, which is not how it works. We always use the previous state o/p to produce the next state.

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i guess its because the clock signals are parallel, i.e. all clock signals hit the ff's at the same time.

Answer 2

A clock cycle time should be large enough that all flip-flops can come in to a stable state before the next clock cycle starts
(or) from the time we provide the input and till the moment output is available will be a cycle.
Suppose cycle 1 is just completed and cycle 2 is just about to start:
1. to reach the result of q0Λ1 to J1K1 it needs $10 ns$
2. to reach the result of (q0Λ1)ΛQ1 to J2K2, other 10 nanoseconds are needed.
3. Now, we need other 10  nanoseconds to operate flipflops as the propagation delay of each flip flop is 10ns.
4. Finally, we need 10 more nanoseconds to get the output from the last AND gate.

For better understanding we can enclose this circuit in a box with one input-pin and one output-pin out, when we provide input to the box, we need at least 40ns to get the output.

Answer should be (1/(2*10ns + 10ns + 10ns) = $\frac{1}{40ns} = 25MHZ$.

Comments

@Manu Thakur Why clock is required for last Nand Gate, it can work even without clock pulse being active

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Since, it's a synchronous counter, all the flip flops will get clock at the same time. Also, All AND gates will get the input simultaneously. I think you shouldn't consider it in serial manner.

$T_{CLK}>= T_{FF}+T_{AND}$

$T_{CLK}>=10+10$

$T_{CLK}>=20\ ns$

$f=\frac{1}{T_{CLK}}=\frac{1}{20\ ns}=50\ Mhz$

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Question asks " maximum clock frequency at which the Counter can be operated" so we need only output of q0q1q2 . we dont need to consider the last AND gate 

Answer 3

As all flip flop are connected to common clock so it is Synchronous Counter
all flip flop changes simultaneously
and there are 3 AND gates
For last FF input will be avail after 2(AND gate)*10

So Frequency = $\frac{1}{t_{ff} + 2t_{and}}$
                    = $\frac{1}{10 + 20}$
                    = 0.033 = 33.33MHz

Comments

The answer would be 1/20 because 2nd AND GATE do not have to wait for getting the output of first AND GATTE.

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why ? it will depend .

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@bikram sir please describe the answer ....

Answer 4

So at all I have concluded , it had asked maximum clock frequency .

And as freq=1/Time period

So we will take best case .

As it is synchronous circuit than all flip flop activate simultaneously and here key is

"Maximum clock frequency at which the counter in the figure below can be operated."

So 1FF+1AND GATE =20 NS

1/20=50 MHZ.

Comments

I also thought the same way, please confirm if it is right answer.

Answer 5

This is what I think is the reason for 30ns.

Let x = $Q_{0}$

[(x)*$Q_{1}$ + (x’)*$Q_{1}$]*x = x*$Q_{1}$ = y(say)

[(y)*$Q_{2}$ + (y’)*$Q_{2}$]*y = y*$Q_{2}$ = z(say)

Now to get Z = $Q_{0}$ * $Q_{1}$ * $Q_{2}$ 

After 10ns we have $Q_{0}$ with us.

and each AND gate require 10ns, so total time = 10ns + 10ns + 10ns = 30ns.

Comments

@Deepak Poonia sir, @GO Classes sir, @Godlike bro is this correct.