GATE CSE 1991 | Question: 06,a

Question

Using $\text{D}$ flip-flop gates, design a parallel-in/serial-out shift register that shifts data from left to right with the following input lines:

1. Clock $\text{CLK}$

2. Three parallel data inputs $A, B, C$

3. Serial input $S$

4. Control input $\text{LOAD} / \overline{\text{SHIFT}}$.

Comments

is this question still relevent?

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https://youtu.be/i3wXLye6LpM?si=resavhsXuVgYajix

Answer 1

Note that iii) Serial input S means that we want output line which gives serial output

Comments

If the output loops back into the circuit, won't it just feed the same sequence back into the circuit?
The question asks for only a serial input S and for the output to be shifted out serially, instead of looping it back in.

Answer 2

Refer the Logic diagram for the  parallel-in/serial-out SHIFT REGISTER, using D flip-flop gates that shifts data from left to right in this video : https://youtu.be/7LmBcGiiYwk