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A  $3 \times 8$ decoder with two enables inputs is to be used to address 8 blocks of memory. What will be the size of each memory block when addressed from a sixteen-bit bus with two MSBs used to enable the decoder? 

$i)2k$                                           $ii)4k$                                       $iii)16k$                                     $iv) 64k$


What does “two enable inputs is to be used” mean? I am not able to visualize the circuit.

in Digital Logic
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$2K ??$
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yes, please explain
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Sorry for the delay.

Here, there are 16-bit bus addresses, So we can represent  $64 K$.

But two bit is used to enable the decoder. It left $16 K $.There are 8 blocks. So, the size of each block will $2K$.
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How 2 bits just for enabling? Can you please draw circuit for the same? It will help me understand the question
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Yes please provide a rough sketch of the circuit @kumar.dilip :(

I have this one and I don't understand how to proceed

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ok, I will try.
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Is it like this..?

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1 Answer

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Ok ....... have this might be it work .....

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