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MadeEasy Test Series: Digital Logic - Decoder

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A  $3 \times 8$ decoder with two enables inputs is to be used to address 8 blocks of memory. What will be the size of each memory block when addressed from a sixteen-bit bus with two MSBs used to enable the decoder? 

$i)2k$                                           $ii)4k$                                       $iii)16k$                                     $iv) 64k$

What does “two enable inputs is to be used” mean? I am not able to visualize the circuit.

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