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Consider addition in two's complement arithmetic. A carry from the most significant bit does not always correspond to an overflow. Explain what is the condition for overflow in two's complement arithmetic.
asked in Digital Logic by Veteran (59.5k points)
edited by | 477 views
+1
$Remark:$
if the sign bit of both the signed numbers is not same as the sign bit of the product, then there is an overflow.

3 Answers

+11 votes
Best answer
XOR of $C_{in}$ with $C_{out}$ of the MSB position.
answered by Boss (30.8k points)
edited by
0
$C_{out} \bigoplus C_{in} = 1 (Overflow) $

$C_{out} \bigoplus C_{in} = 0 ( No Overflow)$
+8 votes

(a) In 2's complement addition Overflow happens only when :

  • Sign bit of two input numbers is 0, and the result has sign bit 1.
  • Sign bit of two input numbers is 1, and the result has sign bit 0.
answered by Boss (34k points)
+1

In 4 bits representation, 

$-3$ 1101 (2's complement of $-3$) $+$

$-2$ 1110 (2's complement of $-2$)


$-5$ 1011 (2's complement of $-5$)

This is an example where there is carry from MSB  but still there is no overflow. Is this right?

0
0 votes
FOR overflow to happen during addition of two number in 2's complement form they must have same sign and result is of opposite sign

(+A) + (+B)= -C

(-A) + (-B)= +C
answered by (315 points)


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