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Boolean algebra. Combinational and sequential circuits. Minimization. Number representations and computer arithmetic (fixed and floating point)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2024-1} & \textbf{2024-2}  & \textbf{2023}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 2&2&2&1&2&3&1&2&3
\\\hline\textbf{2 Marks Count} & 2&2&2&2&2&2&2&2&2
\\\hline\textbf{Total Marks} & 6&6&6&5&6&7&\bf{5}&\bf{6}&\bf{7}\\\hline
\end{array}}}$$

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Recent questions in Digital Logic

0 votes
1 answer
2481
Size of a output of combinational circuit
A combinational circuit is designed to multiply the input by 9. The input is 4 bit BCD and the output is binary. How many output lines are required?
A combinational circuit is designed to multiply the input by 9. The input is 4 bit BCD and the output is binary. How many output lines are required?
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1 votes
0 answers
2482
Gate 2016 Set1
We want to design a synchronous counter that counts the sequence 0-1-0-2-0-3 and then repeats. The minimum number of J-K flip-flops required to implement this counter is
We want to design a synchronous counter that counts the sequence 0-1-0-2-0-3 and then repeats. The minimum number of J-K flip-flops required to implement this counter is
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9 votes
1 answer
2483
Counters+Frequency
___________ $\text{kHz}$ is the sum of frequencies at the points $a, b,c \text{ and } d$.
___________ $\text{kHz}$ is the sum of frequencies at the points $a, b,c \text{ and } d$.
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0 votes
0 answers
2484
Floating point number
Is question missing some data??? i am not able to figure out the exponent
Is question missing some data??? i am not able to figure out the exponent
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8 votes
1 answer
2485
Radix+Quadratic equation
The radix of the number invovled in quadratic equation is, $x^2-10x+39=0$, if the solutions to the quadratic equation is $6$ and $9$ $12$ $13$ $15$ $9$
The radix of the number invovled in quadratic equation is, $x^2-10x+39=0$, if the solutions to the quadratic equation is $6$ and $9$$12$$13$$15$$9$
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6 votes
3 answers
2486
Minimum number of two input NAND gates required to realize the logic circuit
The truth table for the combinational circuit is shown below: What is the minimum number of two input NAND gates required to realize this logic circuit?
The truth table for the combinational circuit is shown below:What is the minimum number of two input NAND gates required to realize this logic circuit?
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2 votes
1 answer
2487
Digital
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2 votes
1 answer
2488
MADE EASY TEST SERIES
The maximum number of Boolean expressions that can be formed for the function f(x, y, z) satisfying the relation f(x,y,z) = f(x,y,z) is ___________.
The maximum number of Boolean expressions that can be formed for the function f(x, y, z) satisfying the relation f(x,y,z) = f(x,y,z) is ___________.
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8 votes
4 answers
2489
MADE EASY TEST SERIES
Consider a clocked sequential circuit as shown in the figure below. Assuming initial state to be Q1 Q0 = 00 For an input sequence X = 1010, the respective output sequence will be _______.
Consider a clocked sequential circuit as shown in the figure below. Assuming initial state to be Q1 Q0 = 00For an input sequence X = 1010, the respective output sequence ...
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1 votes
3 answers
2490
MADE EASY TEST SERIES
What will be the output of multiplexer shown below ?
What will be the output of multiplexer shown below ?
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1 votes
2 answers
2491
2's complement
$2’s$ complements representation of the following decimal number $-(105.75)_{10}$ is: $10010110.01$ $10011110.01$ $10001110.10$ $11001011.10$
$2’s$ complements representation of the following decimal number $-(105.75)_{10}$ is:$10010110.01$$10011110.01$$10001110.10$$11001011.10$
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1 votes
1 answer
2492
..
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1 votes
1 answer
2493
..
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0 votes
1 answer
2494
MADE EASY TEST SERIES
The 4 bit shift register is initialized to value 1000 for (Q3, Q2, Q1, Q0). The D input is derived from the Q0, Q2 and Q3 through two XOR gates as shown in figure below. The pattern 0001 will appear at pulse __________ .
The 4 bit shift register is initialized to value 1000 for (Q3, Q2, Q1, Q0). The D input is derived from the Q0, Q2 and Q3 through two XOR gates as shown in figure below. ...
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1 votes
1 answer
2495
MADE EASY TEST SERIES
Consider the following synchronous counter made up of J-K, D and T Flip-Flops. If the initial state (Q2 Q1 Q0) of the counter is 101, then the state (Q2 Q1 Q0) after 4 clock pulses is _________.
Consider the following synchronous counter made up of J-K, D and T Flip-Flops.If the initial state (Q2 Q1 Q0) of the counter is 101, then the state (Q2 Q1 Q0) after 4 clo...
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2 votes
1 answer
2496
#testbook_digital
Both option C and D is correct Option C , self dual of option C is (x+y).(y+z).(z+x)=xy+yz+zx Option D , self dual of option D is xy+yz+zx=(x+y).(y+z).(z+x) Both hold the property of self dual
Both option C and D is correctOption C , self dual of option C is (x+y).(y+z).(z+x)=xy+yz+zxOption D , self dual of option D is xy+yz+zx=(x+y).(y+z).(z+x)Both hold the pr...
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1 votes
1 answer
2497
#testbook_digital
my sol to truth table is Y=A'B+AB=B both opyion B and C satisfied it option B , AB+B=(A+1)B=B option C, A'B+B=(A'+1)B=B
my sol to truth table is Y=A'B+AB=Bboth opyion B and C satisfied itoption B , AB+B=(A+1)B=Boption C, A'B+B=(A'+1)B=B
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0 votes
1 answer
2500
#virtual gate
option A) 00 B) 10 C) 11 D) state 11 is not recahable
option A) 00 B) 10 C) 11 D) state 11 is not recahable
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