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A priority encoder accepts three input signals $\text{(A, B and C)}$ and produces a two-bit output $(X_1, X_0 )$ corresponding to the highest priority active input signal. Assume $A$ has the highest priority followed by $B$ and $C$ has the lowest priority. If none of the inputs are active the output should be $00$, design the priority encoder using $4:1$ multiplexers as the main components.

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Best answer
49 49 votes

$\text{MSB} - \text{Most Significant Bit}$
$\text{LSB} - \text{Least Significant Bit}$

$\begin{array}{ccccc}
\rlap{\text{TRUTH TABLE}} \\
\rlap{\text{Inputs}: A,B,C}\\
\rlap{\text{Outputs}: \text{MSB},\text{LSB}}\\
A &B&C&\quad\text{MSB}&\text{LSB}\\
0&0&0&0&0\\
0&0&1&0&1\\
0&1&X&1&0\\
1&X&X&1&1\\\hline
\end{array}$

$\text{MSB} = A+B$
$\text{LSB} =A + \bar B C$ 

 

It can be implemented using two $4 \times 1$ Multiplexers.

edited by
9 9 votes

We can implement the priority encoder using two $4:1$. Multiplexers as main components and $1$ NOT gate and $1$ OR gate
Using following truth table (Priority encoder with highest priority to $A$)$$\begin{array}{cccc|cc}  \textbf{A} & \textbf {B} &\textbf {C} & \textbf {X} &  \textbf{$X_1$ } & \textbf{$X_0$}\\ \hline 0& 0& 0  & \text{X} &0 &0\\ 0& 0& 1  & \text{X} &0 &1\\  0& 1& \text{X} & \text{X} &1 &0 \\ 1& \text{X}& \text{X}  & \text{X} &1 &1 \\ \end{array}$$

edited by
3 3 votes

we know the truth table of priority encoder .

now we have a multiplexer. we need to do selection in a abnormal way. means we have to play with select lines . and we have 2 output from the above function. relize them and then give input to the select line of muxs.

y1= i3+i2

y0=i3+ i2' i1

now make y1 as s1 select line .and y0 as s0.

0 0 votes

$X_0 = \bar{A} \bar{B} C + A$

$X_1 = \bar{A} B  + A$

 

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