GATE CSE 2001 | Question: 2.8

Question

Consider the following circuit with initial state $Q_0 = Q_1 = 0$. The D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times $0.$

Consider the following timing diagrams of X and C. The clock period of $C \geq 40$ nanosecond. Which one is the correct plot of Y?

      

• A.
• B.
• C.
• D.

Comments

CRUX of this question lies in the second positive edge!!

At the second positive edge: this is happening ->
X=1 and Q0` is changing from 1->0. so what should be considered here?
=> When second positive edge arrives, Q0` would surely be 1 for at least 20 more seconds (set up time) before transitioning from 1 to 0. Hence answer: opt A
 

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Setup time is the minimum amount of time the input data must be stable before the active clock edge, ensuring the data is properly captured.

Hold time is the minimum amount of time the input data must remain stable after the active clock edge, preventing the data from being accidentally changed by subsequent signals

 

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Complete & Easy Explanation of Hold time, Setup time with Many Examples & GATE PYQs: https://youtube.com/playlist?list=PLIPZ2_p3RNHi3p3cDBRInTHCJeITrkTFn

Answer 1

Answer is (a).

Given clock is $+$ edge triggered. 

See the first positive edge. $X$ is $0$, and hence, the output is $0$. $Q_0$ is $0$ and $Q_0'$ is $1$. 

Second $+$ edge, $X$ is $1$ and $Q_0'$ is also $1.$ So, output is $1.$ (When second positive edge of the clock arrives, $Q_0'$ would surely be $1$ because the setup time of flip-flop is given as $20$ ns and the clock period is $\geq 40$ $ns$)

Third $+$ edge, $X$ is $1$ and $Q_0'$ is $0,$ So, output is $0.$ $(Q_0'$ becomes $0$ before the third positive edge, but output $Y$ would not change as the flip-flop is positive edge triggered)

Now, output never changes back to $1$ as $Q_0'$ is always $0$ and when $Q_0'$ finally becomes $1, X$ is $0.$ 

Set up time and hold times are given just to ensure that edge triggering works properly.

Comments

@arjun sir

please tell me where to study the theory to solve these timing diagram related questions ?

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When second positive edge of the clock arrives, Q′0 would surely be 1 because the setup time of flip-flop is given as 20 ns and the clock period is ≥40 ns

Here this line means if X had transitioned (0->1) after first negative edge then flip flop will not be able to work properly(as setup time will is 20 ns). Please correct me if I’m wrong.

https://www.youtube.com/watch?v=64DWUzNHH1o

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Can anyone please clearly explain the second + edge paragraph

Answer 2

Setup Time

Minimum amount of time BEFORE the clock's active edge that the data must be stable for it to be latched correctly

Hold Time

Minimum amount of Time AFTER the clock's active edge during which data must be stable

• Setup and Hold time measured with respect to active clock edge

Read This

• Initial state 
         $Q_0=Q_1=0$ (given)
         Setup Time   = 20ns
         Hold Time    = 0ns
         Clock Period = 40ns
• Behaviour of Flip Flp depends on setup time and hold time
• Flip Flop responds to the input during +ve edge but it consider the stable input which was given even before setup time
• Flip-Flop changes its output to stable state within hold time
   

• Above input will not be considered in the immediate +ve edge but it will be considered in the next coming +ve edge
• In our Question $\color{Red} X$ goes to $0\rightarrow1$ before stable time which get considered in the immediate +ve edge

• From the truth table it is clear that $Q_1$ is HIGH at $ \color{Blue}{ \text{clock } 1}$ only

Comments

@pC in truth table , for clock=1 , D1=D0.(Q0)'=1.0=0 plz verify

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Btw clock 0 and Clock 1 ===> the i/p of D1 changed to 1 ( due to AND gate shows immediate effect )

after applying the Clock 1 ===> Q0 =1 and Q1 = 1

 

Btw clock 1 and Clock 2 ===> the i/p of D1 changed to 0

after applying the Clock 2 ===> Q0 =1 and Q1 = 0

 

Btw clock 2 and Clock 3 ===> the i/p of D1 is 0

after applying the Clock 3 ===> Q0 =1 and Q1 = 0

 

etc

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thanks

very clear explanation :)

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What if the input changes during each and every setup time? Will the output never change? Like for example think, that input changes from +ve to -ve and -ve to +ve just before the positive edge triggers in the given example. What will happen in that situation?

Answer 3

Modifications or corrections to the timing diagram are welcomed.

Comments

@tanaya Can you answer my doubt- What if the input changes during each and every setup time? Will the output never change? Like for example think, that input changes from +ve to -ve and -ve to +ve just before the positive edge triggers (all of them) in the given example. What will happen in that situation?

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https://electronics.stackexchange.com/questions/347499/setup-and-hold-time-output-when-violated/347506#347506

This might help. 

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tanaya

before the 6^th clock cycle the input is not stable within the setup time , thus no change is shown in the timing diagram for  Qo’ ? in such case we should continue the previous value?

Answer 4

y is 1 only at 2nd +ve edge

Comments

MRINMOY_HALDER  what is Qon in your answer?

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If Q0 is current state then Qon is next state.

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ok thank you

Answer 5

Final Answer is option A

Comments

nice explanation

Answer 6

answer - C

initially Q₀' is 1

for the first clock period nothing will change since input doesn't come before rising edge of the clock cycle

Q₀' will only go to 0 on rising edge of next clock cycle

for only one clock cycle D1 will be 1 and hence Y

Comments

But once Q1 becomes 1 it should become 0 only on the next rising edge of clock rt? That is after an entire clock period as in option (A)