Consider the following circuit with initial state $Q_0 = Q_1 = 0$. The D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times $0.$

Consider the following timing diagrams of X and C. The clock period of $C \geq 40$ nanosecond. Which one is the correct plot of Y?

## 5 Answers

Answer is **(a). **

Given clock is $+$ edge triggered.

See the first positive edge. $X$ is $0$, and hence, the output is $0$. $Q_0$ is $0$ and $Q_0'$ is $1$.

Second $+$ edge, $X$ is $1$ and $Q_0'$ is also $1.$ So, output is $1.$ (When second positive edge of the clock arrives, $Q_0'$ would surely be $1$ because the setup time of flip-flop is given as $20$ ns and the clock period is $\geq 40$ $ns$)

Third $+$ edge, $X$ is $1$ and $Q_0'$ is $0,$ So, output is $0.$ $(Q_0'$ becomes $0$ before the third positive edge, but output $Y$ would not change as the flip-flop is positive edge triggered)

Now, output never changes back to $1$ as $Q_0'$ is always $0$ and when $Q_0'$ finally becomes $1, X$ is $0.$

Set up time and hold times are given just to ensure that edge triggering works properly.

### 21 Comments

Second + edge, X is 1 and Q_{0}' is also one. So, output is 1. (When second positive edge of the clock arrives, Q_{0}' would surely be 1 because the setup time of flip-flop is given as 20 ns and the clock period is >= 40 ns)

@Arjun Sir Why the qo' is 1 in second +ve edge. Please explain it more briefly.

When second positive edge of the clock arrives,

Q′0 would surely be 1 because the setup time of flip-flop is given as 20 ns and the clock period is ≥40ns

Here this line means if X had transitioned (0->1) after first negative edge then flip flop will not be able to work properly(as setup time will is 20 ns). Please correct me if I’m wrong.

**Setup Time**

Minimum amount of time BEFORE the clock's active edge that the data must be stable for it to be latched correctly

**Hold Time**

Minimum amount of Time AFTER the clock's active edge during which data must be stable

- Setup and Hold time measured with respect to active clock edge

Read This

- Initial state

$Q_0=Q_1=0$ (given)

Setup Time = 20ns

Hold Time = 0ns

Clock Period = 40ns - Behaviour of Flip Flp depends on setup time and hold time
- Flip Flop responds to the input during +ve edge but it consider the stable input which was given even before setup time
- Flip-Flop changes its output to stable state within hold time

- Above input will not be considered in the immediate +ve edge but it will be considered in the next coming +ve edge
- In our Question $\color{Red} X$ goes to $0\rightarrow1$ before stable time which get considered in the immediate +ve edge

- From the truth table it is clear that $Q_1$ is
**HIGH**at $ \color{Blue}{ \text{clock } 1}$ only

### 4 Comments

Btw clock 0 and Clock 1 ===> the i/p of D1 changed to 1 ( **due to AND gate shows immediate effect **)

after applying the Clock 1 ===> Q0 =1 and Q1 = 1

Btw clock 1 and Clock 2 ===> the i/p of D1 changed to 0

after applying the Clock 2 ===> Q0 =1 and Q1 = 0

Btw clock 2 and Clock 3 ===> the i/p of D1 is 0

after applying the Clock 3 ===> Q0 =1 and Q1 = 0

etc

### 10 Comments

Hi @tanaya ji, Thanks for valuable effort.

Notice change appears in $Q_{0}$ and $Q_{1}$ when clock is positively triggered. But $D_{1}$ does not depend on clock triggering(means $D_{1}$ can change any time if it's I/P changes).