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The below figure shows four D-type flip-flops connected as a shift register using a $XOR$ gate. The initial state and three subsequent states for three clock pulses are also given.

 

State $Q_{A}$ $Q_{B}$ $Q_{C}$ $Q_{D}$
Initial $1$ $1$ $1$ $1$
After the first clock $0$ $1$ $1$ $1$
After the second clock $0$ $0$ $1$ $1$
After the third clock $0$ $0$ $0$ $1$

The state $Q_{A} Q_{B} Q_{C} Q_{D}$ after the fourth clock pulse is

  1. $0000$
  2. $1111$
  3. $1001$
  4. $1000$
in Digital Logic
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3 Answers

11 votes
 
Best answer
Option (D) $\mathbf{1000}$
$Q_{AN} =Q_{C} \bigoplus  Q_{D}, \ Q_{ABN} = Q_{A}, Q_{CN}=Q_{B} \ \text{and} \ Q_{DN}=Q_{C}$
$$\begin{array}{|c|c|c|c|} \hline \bf{Q_A} & \bf {Q_B}& \bf {Q_C} &  \bf{Q_D }\\\hline1&1&1&1\\ 0&1&1&1\\0&0&1&1\\ 0&0&0&1 \\ \mathbf{1}&\mathbf{0} &\mathbf{0}&\mathbf{0}\\\hline\end{array}$$

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0
Bro here after 4 the clock pulse it should be 0000 na because in the question he gave that table after 1 clock cycle and so on so why did u take here 5 clock output plz clear
10

Bro, u can see this...

1 vote

All have D flip-flops:

QB, QC and QD are depending on the previous states of QA, QB and QC respectively.

only QA is depending on previous XOR of QC and QD

So, the next state:

QA = XOR (prev QC and prev QD)= 1

QB = prev of QA = 0

QC = prev of QB = 0

QD = prev of QC = 0

Ans: 1000

0 votes

$$\begin{array}{|c|c|c|c|c|c|c|c|c|c|} \hline \bf{CP} & \bf {Q_A}& \bf {Q_B} &  \bf{Q_C }&  \bf{Q_D }&  \bf{Q_A^+=Q_C\oplus Q_D }&  \bf{Q_B^+=Q_A }&  \bf{Q_C^+=Q_B }&  \bf{Q_D^+=Q_C }&  \bf{CP}\\\hline0&1&1&1&1&0&1&1&1&1\\ 1&0&1&1&1&0&0&1&1&2\\ 2&0&0&1&1&0&0&0&1&3 \\ 3&0&0&0&1&\mathbf{1}&\mathbf{0}&\mathbf{0}&\mathbf{0}&\mathbf{4}\\\hline\end{array}$$

Correct Answer (D)

Answer:

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