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15
votes
1
answer
1
How to find number of swappings in bubble sort in least possible time ( any shortcut available )
1. The number of swappings needed to sort the numbers: 8, 22, 7, 9, 31, 19, 5, 13 in ascending order using bubble sort is- (a) 11 (b) 12 (c) 13 (d) 14 I know how to solve it using ... I did was to write every pass and check the swappings. But , it takes too much time. Is there any shortcut possible ?
1. The number of swappings needed to sort the numbers: 8, 22, 7, 9, 31, 19, 5, 13 in ascending order using bubble sort is—(a) 11 (b) 12(c) 13 (d) 14I know how to solve ...
worst_engineer
167k
views
worst_engineer
asked
Aug 2, 2015
Algorithms
sorting
algorithms
bubble-sort
+
–
89
votes
7
answers
2
GATE CSE 2004 | Question: 23, ISRO2007-32
Identify the correct translation into logical notation of the following assertion. Some boys in the class are taller than all the girls Note: $\text{taller} (x, y)$ is true if $x$ is taller than $y$ ... $(\exists x) (\text{boy}(x) \land (\forall y) (\text{girl}(y) \rightarrow \text{taller}(x, y)))$
Identify the correct translation into logical notation of the following assertion.Some boys in the class are taller than all the girlsNote: $\text{taller} (x, y)$ is true...
Kathleen
132k
views
Kathleen
asked
Sep 18, 2014
Mathematical Logic
gatecse-2004
mathematical-logic
easy
isro2007
first-order-logic
+
–
19
votes
1
answer
3
GATE CSE 1995 | Question: 20
The head of a moving head disk with $100$ tracks numbered $0$ to $99$ is currently serving a request at track $55$. If the queue of requests kept in FIFO order is $10, 70, 75, 23, 65$ which of the two disk scheduling algorithms ... Come First Served) and SSTF (Shortest Seek Time First) will require less head movement? Find the head movement for each of the algorithms.
The head of a moving head disk with $100$ tracks numbered $0$ to $99$ is currently serving a request at track $55$. If the queue of requests kept in FIFO order is $$10, 7...
Kathleen
123k
views
Kathleen
asked
Oct 8, 2014
Operating System
gate1995
operating-system
disk-scheduling
normal
descriptive
+
–
19
votes
3
answers
4
How to construct an automata with even number of a's and odd number of b's?
The alphabets are a and b. Construct a DFA
The alphabets are a and b.Construct a DFA
Gourab_Classic
111k
views
Gourab_Classic
asked
Mar 14, 2016
Theory of Computation
minimal-state-automata
theory-of-computation
finite-automata
combinatory
+
–
16
votes
6
answers
5
Simplified Boolean expression for A'BC+AB'C'+A'B'C'+AB'C+ABC
Simplified Boolean expression for A'BC+AB'C'+A'B'C'+AB'C+ABC A . AB B . B'C C . AB+(A'+AB')C D . AB'+BC+B'C'
Simplified Boolean expression for A'BC+AB'C'+A'B'C'+AB'C+ABCA . ABB . B'CC . AB+(A'+AB')CD . AB'+BC+B'C'
shekhar chauhan
103k
views
shekhar chauhan
asked
Jun 29, 2016
Digital Logic
digital-logic
boolean-algebra
+
–
1
votes
7
answers
6
The maximum number of nodes on level i of a binary tree
Level of a node is distance from root to that node. For example, level of root is 1 and levels of left and right children of root is 2. The maximum number of nodes on level i of a binary tree is In the following answers, the operator '^' indicates power a) 2^i-1 b)2^i c)2^i+1 d)2^(i+1/2)
Level of a node is distance from root to that node. For example, level of root is 1 and levels of left and right children of root is 2. The maximum number of nodes on lev...
Akanksha Kesarwani
102k
views
Akanksha Kesarwani
asked
Jan 16, 2016
DS
binary-tree
data-structures
+
–
4
votes
2
answers
7
Pankaj and Mythili were both asked to write the code to evaluate the following expression
Pankaj and Mythili were both asked to write the code to evaluate the following expression: $a - b + c/(a-b) + (a-b)^2 $ Pankaj writes the following code statements (Code A): print (a-b) + c/(a-b) ... Code B Code A uses more memory and is faster than Code B Code A uses more memory and is slower than Code B
Pankaj and Mythili were both asked to write the code to evaluate the following expression: $$a - b + c/(a-b) + (a-b)^2 $$Pankaj writes the following code statements (Code...
Arjun
96.8k
views
Arjun
asked
Aug 31, 2014
Compiler Design
compiler-design
normal
code-optimization
+
–
4
votes
4
answers
8
NIELIT 2016 DEC Scientist B (CS) - Section B: 16
Two main measures for the efficiency of an algorithm are: Processor and Memory Complexity and Capacity Time and Space Data and Space
Two main measures for the efficiency of an algorithm are:Processor and MemoryComplexity and CapacityTime and SpaceData and Space
admin
85.0k
views
admin
asked
Mar 31, 2020
Algorithms
nielit2016dec-scientistb-cs
algorithms
time-complexity
+
–
68
votes
4
answers
9
Minimum NAND/NOR Gates - Realization for ExOR,ExNor,Adder,Subtractor
Minimum No of Gates NAND/NOR Ex-OR Ex-Nor Half Adder Half Subtractor Full Adder Full Subtractor NAND ? ? ? ? ? ? NOR ? ? ? ? ? ?
Minimum No of Gates NAND/NOR Ex-OREx-NorHalf AdderHalf SubtractorFull AdderFull SubtractorNAND??????NOR??????
bahirNaik
82.7k
views
bahirNaik
asked
Dec 17, 2015
Digital Logic
digital-logic
min-no-gates
+
–
71
votes
5
answers
10
GATE CSE 2010 | Question: 30
Suppose the predicate $F(x, y, t)$ is used to represent the statement that person $x$ can fool person $y$ at time $t$. Which one of the statements below expresses best the meaning of the formula, $\qquad∀x∃y∃t(¬F(x,y,t))$ Everyone can ... time No one can fool everyone all the time Everyone cannot fool some person all the time No one can fool some person at some time
Suppose the predicate $F(x, y, t)$ is used to represent the statement that person $x$ can fool person $y$ at time $t$.Which one of the statements below expresses best the...
gatecse
82.5k
views
gatecse
asked
Sep 21, 2014
Mathematical Logic
gatecse-2010
mathematical-logic
easy
first-order-logic
+
–
278
votes
14
answers
11
GATE CSE 2008 | Question: 67
A processor uses $36$ bit physical address and $32$ bit virtual addresses, with a page frame size of $4$ Kbytes. Each page table entry is of size $4$ bytes. A three level page table is used for virtual to physical address translation, where the virtual address is used as ... tables are respectively $\text{20,20,20}$ $\text{24,24,24}$ $\text{24,24,20}$ $\text{25,25,24}$
A processor uses $36$ bit physical address and $32$ bit virtual addresses, with a page frame size of $4$ Kbytes. Each page table entry is of size $4$ bytes. A three level...
Kathleen
77.5k
views
Kathleen
asked
Sep 12, 2014
Operating System
gatecse-2008
operating-system
virtual-memory
normal
+
–
151
votes
18
answers
12
GATE CSE 2017 Set 2 | Question: 44
Two transactions $T_1$ and $T_2$ are given as $T_1:r_1(X)w_1(X)r_1(Y)w_1(Y)$ $T_2:r_2(Y)w_2(Y)r_2(Z)w_2(Z)$ where $r_i(V)$ denotes a $\textit{read}$ operation by transaction $T_i$ on a variable $V$ and $w_i(V)$ denotes a ... by transaction $T_i$ on a variable $V$. The total number of conflict serializable schedules that can be formed by $T_1$ and $T_2$ is ______
Two transactions $T_1$ and $T_2$ are given as$T_1:r_1(X)w_1(X)r_1(Y)w_1(Y)$$T_2:r_2(Y)w_2(Y)r_2(Z)w_2(Z)$where $r_i(V)$ denotes a $\textit{read}$ operation by transaction...
Madhav
73.3k
views
Madhav
asked
Feb 14, 2017
Databases
gatecse-2017-set2
databases
transaction-and-concurrency
numerical-answers
conflict-serializable
+
–
49
votes
4
answers
13
GATE CSE 2001 | Question: 2.21
Consider a machine with $64$ MB physical memory and a $32$-bit virtual address space. If the page size s $4$ KB, what is the approximate size of the page table? $\text{16 MB}$ $\text{8 MB}$ $\text{2 MB}$ $\text{24 MB}$
Consider a machine with $64$ MB physical memory and a $32$-bit virtual address space. If the page size s $4$ KB, what is the approximate size of the page table?$\text{16 ...
Kathleen
67.4k
views
Kathleen
asked
Sep 14, 2014
Operating System
gatecse-2001
operating-system
virtual-memory
normal
+
–
63
votes
12
answers
14
GATE CSE 2005 | Question: 70
Consider a disk drive with the following specifications: $16$ surfaces, $512$ tracks/surface, $512$ sectors/track, $1$ KB/sector, rotation speed $3000$ rpm. The disk is operated in cycle stealing mode whereby whenever one $4$ byte word is ready it is sent ... $40$ nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is: $10$ $25$ $40$ $50$
Consider a disk drive with the following specifications:$16$ surfaces, $512$ tracks/surface, $512$ sectors/track, $1$ KB/sector, rotation speed $3000$ rpm. The disk is op...
Kathleen
65.8k
views
Kathleen
asked
Sep 22, 2014
CO and Architecture
gatecse-2005
co-and-architecture
disk
normal
dma
+
–
39
votes
7
answers
15
GATE CSE 2008 | Question: 23
Which of the following statements is true for every planar graph on $n$ vertices? The graph is connected The graph is Eulerian The graph has a vertex-cover of size at most $\frac{3n}{4}$ The graph has an independent set of size at least $\frac{n}{3}$
Which of the following statements is true for every planar graph on $n$ vertices?The graph is connectedThe graph is EulerianThe graph has a vertex-cover of size at most $...
Kathleen
65.3k
views
Kathleen
asked
Sep 11, 2014
Graph Theory
gatecse-2008
graph-theory
normal
graph-planarity
+
–
129
votes
19
answers
16
GATE CSE 2004 | Question: 47
Consider a system with a two-level paging scheme in which a regular memory access takes $150$ $nanoseconds$, and servicing a page fault takes $8$ $milliseconds$. An average instruction takes $100$ nanoseconds of CPU time, and two memory accesses. ... execution time? $\text{645 nanoseconds}$ $\text{1050 nanoseconds}$ $\text{1215 nanoseconds}$ $\text{1230 nanoseconds}$
Consider a system with a two-level paging scheme in which a regular memory access takes $150$ $nanoseconds$, and servicing a page fault takes $8$ $milliseconds$. An avera...
gatecse
64.5k
views
gatecse
asked
Sep 5, 2014
CO and Architecture
gatecse-2004
co-and-architecture
virtual-memory
normal
+
–
100
votes
12
answers
17
GATE CSE 2015 Set 2 | Question: 48
A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is ... adder is implemented by using four full adders. The total propagation time of this $4$-bit binary adder in microseconds is ______.
A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that o...
go_editor
62.5k
views
go_editor
asked
Feb 13, 2015
Digital Logic
gatecse-2015-set2
digital-logic
adder
normal
numerical-answers
+
–
8
votes
2
answers
18
please tell the multiplication of (+15 X -13) Through the Booth Multiplication Algo.
..
..
LavTheRawkstar
60.9k
views
LavTheRawkstar
asked
Jun 19, 2016
CO and Architecture
booths-algorithm
+
–
58
votes
7
answers
19
GATE IT 2008 | Question: 4
What is the size of the smallest $\textsf{MIS}$ (Maximal Independent Set) of a chain of nine nodes? $5$ $4$ $3$ $2$
What is the size of the smallest $\textsf{MIS}$ (Maximal Independent Set) of a chain of nine nodes?$5$$4$$3$$2$
Ishrat Jahan
59.2k
views
Ishrat Jahan
asked
Oct 27, 2014
Graph Theory
gateit-2008
normal
graph-connectivity
+
–
0
votes
1
answer
20
Which of the following is not a member of a class ?
A. Static function B. Friend Function C. Const Function D. Virtual function
A. Static functionB. Friend FunctionC. Const FunctionD. Virtual function
im.raj
57.5k
views
im.raj
asked
May 6, 2016
Programming in C
programming-in-c
programming
+
–
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