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41
ISRO 2017-ECE Digital Logic
Which of the following statement is true for Programmable Logic array (PLA)? (a) Fixed AND array and Fused programmable OR array (b) Fused programmable AND array and Fixed OR array (c) Fused programmable AND array and Fused programmable OR array (d) None of the above
Which of the following statement is true for Programmable Logic array (PLA)?(a) Fixed AND array and Fused programmable OR array(b) Fused programmable AND array and Fixed ...
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3 votes
1 answer
42
ISRO2016- EC Calculus
Evaluate $\int_0^1 \int_0^{\sqrt{1+x^2}} \frac{d x \cdot d y}{\left(1+x^2+y^2\right)}$ $\frac{\pi}{2}[\log (1+\sqrt{2})]$ $\frac{\pi}{4}[\log (1+\sqrt{2})]$ $\frac{\pi}{2}[\log (1-\sqrt{2})]$ $\frac{\pi}{4}[\log (1-\sqrt{2})]$
Evaluate $\int_0^1 \int_0^{\sqrt{1+x^2}} \frac{d x \cdot d y}{\left(1+x^2+y^2\right)}$$\frac{\pi}{2}[\log (1+\sqrt{2})]$$\frac{\pi}{4}[\log (1+\sqrt{2})]$$\frac{\pi}{2}[\...
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0 votes
2 answers
43
ISRO 2009 -ECE Logic Family
Which of the following technology results in least power dissipation ? a) CMOS b) ECL c) TTL d) NMOS
Which of the following technology results in least power dissipation ?a) CMOSb) ECLc) TTLd) NMOS
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4 votes
1 answer
44
ISRO2013-ECE Digital Logic
If a counter having $10$ flip flops is initially at $0,$ what count will it hold after $2060$ pulses? $000\; 000\; 1100$ $000 \;001\; 1100$ $000 \;001\; 1000$ $000 \;000\; 1110$
If a counter having $10$ flip flops is initially at $0,$ what count will it hold after $2060$ pulses?$000\; 000\; 1100$$000 \;001\; 1100$$000 \;001\; 1000$$000 \;000\; 11...
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0 votes
2 answers
45
ISRO 2007- ECE Half Adder using NAND
The sum S of A and B in a half Adder can be implemented by using K NAND gates. The value of K is a) 3 b) 4 c) 5 d) None of these
The sum S of A and B in a half Adder can be implemented by using K NAND gates. The value of K isa) 3b) 4c) 5d) None of these
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1 votes
0 answers
46
ISRO 2017-ECE Digital logic
Consider following 8085 microprocessor program MVI A, DATA1 ORA A JM DISPLAY OUT PORT1 CMA DISPLAY : ADI 01H OT PORT1 HLT If DATA1 = A7H, the output at PORT1 is (a) A7H (b) 58H (c) 00H (d) 59H
Consider following 8085 microprocessor programMVIA, DATA1ORA AJM DISPLAYOUT PORT1CMADISPLAY :ADI 01HOT PORT1HLTIf DATA1 = A7H, the output at PORT1 is(a) A7H(b) 58H(c) 00H...
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1 answer
47
ISRO 2007-ECE Memory
A memory system of size 16K bytes is required to be designed using memory chips, which have 12 address lines and 4 data lines each. The number of such chips required to design the memory system is a) 2 b) 4 c) 8 d) 16
A memory system of size 16K bytes is required to be designed using memory chips, which have 12 address lines and 4 data lines each. The number of such chips required to d...
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1 answer
49
ISRO 2006-ECE A/D converter
10 bit A/D converters, the quantization error is given by (in percent) a) 1 b) 2 c) 0.1 d) 0.2
10 bit A/D converters, the quantization error is given by (in percent)a) 1b) 2c) 0.1d) 0.2
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0 votes
1 answer
50
ISRO 2007-ECE Boolean Dual
For the identity $AB + A' C + BC = AB + A' C$, the dual form is $(A+B) (A'+C)(B+C)= (A+B)(A'+C)$ $(A'+ B') ( A' + C') (B'+C')= (A'+ B') (A +C')$ $(A+B) (A'+C) (B+C) = (A'+ B') (A+ C')$ $A'B'+AC'+ B'C'= A'B'+AC'$
For the identity $AB + A' C + BC = AB + A' C$, the dual form is$(A+B) (A'+C)(B+C)= (A+B)(A'+C)$$(A'+ B') ( A' + C') (B'+C')= (A'+ B') (A +C')$$(A+B) (A'+C) (B+C) = (A'+ B...
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1 answer
53
ISRO 2017-ECE Minterms
Simplify the below function represented in sum of minterms
Simplify the below function represented in sum of minterms
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2 votes
1 answer
54
ISRO 2010-ECE Digital logic
What is the maximum clock frequency at the given circuit can be operated without timing violations? Assume that the Combinational logic delay is 10 ns and the clock duty cycle varies from 40% to 60 %. a) 100 MHz b) 50 MHz c) 40 MHz d) 25 MHz
What is the maximum clock frequency at the given circuit can be operated without timing violations? Assume that the Combinational logic delay is 10 ns and the clock duty ...
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0 votes
1 answer
55
ISRO 2010-ECE Continuity in functions
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1 answer
57
ISRO 2008-ECE Computer architecture
Digital signal processors use a computer architecture derived from (a) Harvard Architecture (b) Von-Neumann Architecture (c) Cray Architecture (d) None of the above
Digital signal processors use a computer architecture derived from(a) Harvard Architecture(b) Von-Neumann Architecture(c) Cray Architecture(d) None of the above
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1 votes
2 answers
58
ISRO2016-ECE Networks
A typical optical fiber has high refractive index core & low refractive index cladding Low refractive index core & high refractive index cladding Uniform refractive index core surrounded by variable refractive index cladding None of the above
A typical optical fiber hashigh refractive index core & low refractive index claddingLow refractive index core & high refractive index claddingUniform refractive index co...
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2 votes
1 answer
59
ISRO2016-ECE Digital Logic
For a $10$-bit digital ramp ADC using $500\;\text{kHz}$ clock, the maximum conversion time is $2048\; \mu \;\text{S}$ $2046\; \mu \;\text{S}$ $2064\; \mu \;\text{S}$ $2084\; \mu \;\text{S}$
For a $10$-bit digital ramp ADC using $500\;\text{kHz}$ clock, the maximum conversion time is$2048\; \mu \;\text{S}$$2046\; \mu \;\text{S}$$2064\; \mu \;\text{S}$$2084\; ...
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2 votes
2 answers
60
ISRO 2010-ECE Calculus
What does the following integral evaluate to? a) 5 π /16 b) 5 π /8 c) 0 d) 5 π /32
What does the following integral evaluate to?a) 5 π /16b) 5 π /8c) 0d) 5 π /32
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