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Recent questions tagged digital-logic
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Morris Mano Edition 3 Exercise 7 Question 37 (Page No. 305)
An integrated circuit ram chip has a capacity of 1024 words of 8 bits each ($1K \times 8$) How many addresses and the data lines are there in the chips? How many chips are needed to construct a $16K \times 16$ ram? How many ... $1 \times 8$ chips? What are the input to the decoder and where are its output connected?
An integrated circuit ram chip has a capacity of 1024 words of 8 bits each ($1K \times 8$)How many addresses and the data lines are there in the chips?How many chips are ...
ajaysoni1924
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Apr 6, 2019
Digital Logic
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632
Morris Mano Edition 3 Exercise 7 Question 36 (Page No. 305)
A computer uses RAM chips of $1024 \times 1$ capacity. how many chips are needed and how should there address line should be connected to provide a memory capacity of 1024 bytes. how many chips are needed to provide a memory capacity of 16K bytes? Explain in the words how chips are connected.
A computer uses RAM chips of $1024 \times 1$ capacity.how many chips are needed and how should there address line should be connected to provide a memory capacity of 1024...
ajaysoni1924
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Apr 6, 2019
Digital Logic
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ram
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633
Morris Mano Edition 3 Exercise 7 Question 35 (Page No. 305)
How many $128 \times 8$ RAM chips are needed to provide a memory capacity of 2048 bytes? How many lines of the address must be used to access 2048 bytes? How many of these lines are connected to the address inputs of all the chips? How many lines must be decoded for the chip select inputs?Specify the size of the decoder?
How many $128 \times 8$ RAM chips are needed to provide a memory capacity of 2048 bytes?How many lines of the address must be used to access 2048 bytes? How many of these...
ajaysoni1924
662
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Apr 6, 2019
Digital Logic
digital-logic
morris-mano
sequential-circuit
memory-unit
ram
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634
Morris Mano Edition 3 Exercise 7 Question 34 (Page No. 305)
Word number 535 in the memory shown in the figure contains the binary equivalent of 2209. List the 10 bit address and 16-bit memory content of the word.
Word number 535 in the memory shown in the figure contains the binary equivalent of 2209. List the 10 bit address and 16-bit memory content of the word.
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429
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Apr 6, 2019
Digital Logic
digital-logic
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635
Morris Mano Edition 3 Exercise 7 Question 33 (Page No. 305)
The following memory units are specified by the number of words times the number of bits per word. How many address lines and Input output data lines are needed in each case given below? $2K \times 16$; $64K \times 8$; $16M \times 32$; $96K \times 12$;
The following memory units are specified by the number of words times the number of bits per word. How many address lines and Input output data lines are needed in each c...
ajaysoni1924
267
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Apr 6, 2019
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636
Morris Mano Edition 3 Exercise 7 Question 32 (Page No. 305)
Construct a Johnson counter for ten timing signals.
Construct a Johnson counter for ten timing signals.
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Apr 6, 2019
Digital Logic
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637
Morris Mano Edition 3 Exercise 7 Question 31 (Page No. 305)
Complete the design of Johnson counter of the figure showing the output of the eight timing signals using eight AND gates.
Complete the design of Johnson counter of the figure showing the output of the eight timing signals using eight AND gates.
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645
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Apr 6, 2019
Digital Logic
digital-logic
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638
Morris Mano Edition 3 Exercise 7 Question 30 (Page No. 305)
Show the circuit and the timing diagram for generating six repeated timing signals, $T _0$ through $T _5$.
Show the circuit and the timing diagram for generating six repeated timing signals, $T _0$ through $T _5$.
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198
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Apr 6, 2019
Digital Logic
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639
Morris Mano Edition 3 Exercise 7 Question 29 (Page No. 305)
Add four 2-input AND gates to the circuit of the figure. One input in each gate is connected to one output of the decoder. The other input in each gate is connected to the clock. Label the outputs of the AND gate as $P _0,P _1,P _2, and P _3$. Show the timing diagram of the for P outputs.
Add four 2-input AND gates to the circuit of the figure. One input in each gate is connected to one output of the decoder. The other input in each gate is connected to th...
ajaysoni1924
206
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Apr 6, 2019
Digital Logic
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640
Morris Mano Edition 3 Exercise 7 Question 28 (Page No. 305)
Using a start signal as in the figure , construct a word time control that stays on for a period of 16 clock pulses.
Using a start signal as in the figure , construct a word time control that stays on for a period of 16 clock pulses.
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309
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Apr 6, 2019
Digital Logic
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641
Morris Mano Edition 3 Exercise 7 Question 27 (Page No. 305)
Using two circuits of the type shown in the figure, construct a binary counter that counts from 0 through binary 64.
Using two circuits of the type shown in the figure, construct a binary counter that counts from 0 through binary 64.
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333
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Apr 6, 2019
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642
Morris Mano Edition 3 Exercise 7 Question 26 (Page No. 305)
Construct a mod -12 counter using the circuit specified in the figure.
Construct a mod -12 counter using the circuit specified in the figure.
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Apr 6, 2019
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643
Morris Mano Edition 3 Exercise 7 Question 25 (Page No. 305)
Construct a BCD counter using the circuit specified in the figure and a AND gate.
Construct a BCD counter using the circuit specified in the figure and a AND gate.
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317
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Apr 6, 2019
Digital Logic
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644
Morris Mano Edition 3 Exercise 7 Question 24 (Page No. 305)
Show the connection between four IC binary counters with the parallel load to produce a 16-bit binary counter with the parallel load. Use a block diagram for each IC.
Show the connection between four IC binary counters with the parallel load to produce a 16-bit binary counter with the parallel load. Use a block diagram for each IC.
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229
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Apr 6, 2019
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645
Morris Mano Edition 3 Exercise 7 Question 23 (Page No. 304)
Design a synchronous BCD counter with JK flip-flops
Design a synchronous BCD counter with JK flip-flops
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Apr 6, 2019
Digital Logic
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646
Morris Mano Edition 3 Exercise 7 Question 22 (Page No. 304)
verify the flip-flop input functions of the synchronous BCD counter specified in the table given below. Draw the logic diagram of the BCD counter and include a count enable control input.
verify the flip-flop input functions of the synchronous BCD counter specified in the table given below. Draw the logic diagram of the BCD counter and include a count enab...
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ajaysoni1924
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Apr 6, 2019
Digital Logic
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647
Morris Mano Edition 3 Exercise 7 Question 21 (Page No. 304)
Modify the counter given in the figure so that when both the up and down control inputs are equal to 1. the counter does not change state, but remains in the same count.
Modify the counter given in the figure so that when both the up and down control inputs are equal to 1. the counter does not change state, but remains in the same count.
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492
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ajaysoni1924
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Apr 6, 2019
Digital Logic
digital-logic
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648
Morris Mano Edition 3 Exercise 7 Question 20 (Page No. 304)
Design a 4-bit binary synchronous counter with D flip-flops.
Design a 4-bit binary synchronous counter with D flip-flops.
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187
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Apr 6, 2019
Digital Logic
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649
Morris Mano Edition 3 Exercise 7 Question 19 (Page No. 304)
Design a 4-bit ripple counter with D flip-flops.
Design a 4-bit ripple counter with D flip-flops.
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217
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ajaysoni1924
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Apr 6, 2019
Digital Logic
digital-logic
morris-mano
sequential-circuit
digital-counter
ripple-counter-operation
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650
Morris Mano Edition 3 Exercise 7 Question 18 (Page No. 304)
Determine the next state for each of the six unused states in the BCD ripple counter shown in the figure. Determine whether it is self-correcting.
Determine the next state for each of the six unused states in the BCD ripple counter shown in the figure. Determine whether it is self-correcting.
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526
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Apr 6, 2019
Digital Logic
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sequential-circuit
digital-counter
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1
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651
Morris Mano Edition 3 Exercise 7 Question 17 (Page No. 304)
How many flip-flops will be complemented in a 10-bit binary ripple counter to reach the next count after the following count? 1001100111; 0011111111;
How many flip-flops will be complemented in a 10-bit binary ripple counter to reach the next count after the following count?1001100111;0011111111;
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ajaysoni1924
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Apr 6, 2019
Digital Logic
digital-logic
morris-mano
sequential-circuit
digital-counter
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652
Morris Mano Edition 3 Exercise 7 Question 16 (Page No. 304)
A flip-flop has 10 nanosecond delay from the time its CP input goes from 1 to 0 to the time the output is complemented. What is the maximum delay in the 10-bit binary ripple counter that uses these flip-flop? What is the maximum frequency the counter can operate reliably.
A flip-flop has 10 nanosecond delay from the time its CP input goes from 1 to 0 to the time the output is complemented. What is the maximum delay in the 10-bit binary rip...
ajaysoni1924
341
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Apr 6, 2019
Digital Logic
digital-logic
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digital-counter
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653
Morris Mano Edition 3 Exercise 7 Question 15 (Page No. 304)
Construct a BCD ripple counter using a 4-bit binary ripple counter that can be cleared asynchronously and an external NAND gate.
Construct a BCD ripple counter using a 4-bit binary ripple counter that can be cleared asynchronously and an external NAND gate.
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Apr 6, 2019
Digital Logic
digital-logic
morris-mano
sequential-circuit
digital-counter
ripple-counter-operation
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654
Morris Mano Edition 3 Exercise 7 Question 14 (Page No. 304)
Draw the logic diagram of a 4-bit binary ripple down counter using the following. Flip-flops that trigger on the positive edge transition of the clock. Flip-flop that trigger on the negative edge transition of the clock.
Draw the logic diagram of a 4-bit binary ripple down counter using the following.Flip-flops that trigger on the positive edge transition of the clock.Flip-flop that trigg...
ajaysoni1924
255
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ajaysoni1924
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Apr 6, 2019
Digital Logic
digital-logic
morris-mano
sequential-circuit
digital-counter
ripple-counter-operation
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655
Morris Mano Edition 3 Exercise 7 Question 13 (Page No. 304)
Draw the logic diagram of a 4-bit binary ripple counter using flip-flops that trigger on the positive-edge transition.
Draw the logic diagram of a 4-bit binary ripple counter using flip-flops that trigger on the positive-edge transition.
ajaysoni1924
221
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ajaysoni1924
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Apr 6, 2019
Digital Logic
digital-logic
morris-mano
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656
Morris Mano Edition 3 Exercise 7 Question 12 (Page No. 304)
It was stated that the 2's complement of a binary number can be formed by lowing all the least significant 0's and the first 1 unchanged and complementing all the other higher significant bits, Design a serial 2's complementer using this procedure. The ... the unchanged bits($ x \oplus 0 = x$) or complement the bits ($ x \oplus 1 = x'$).
It was stated that the 2’s complement of a binary number can be formed by lowing all the least significant 0’s and the first 1 unchanged and complementing all the oth...
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Apr 6, 2019
Digital Logic
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registers
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657
Morris Mano Edition 3 Exercise 7 Question 11 (Page No. 304)
what changes are needed to the figure to convert it to a serial subtractor that subtracts the content of register B from the content of register A?
what changes are needed to the figure to convert it to a serial subtractor that subtracts the content of register B from the content of register A?
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671
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Apr 6, 2019
Digital Logic
digital-logic
morris-mano
sequential-circuit
serial-adder
registers
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2
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0
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658
Morris Mano Edition 3 Exercise 7 Question 10 (Page No. 304)
The serial adder of the figure uses 4-bit registers. Register A holds binary number 0101 and register B holds 0111. The carry flip-flop is initially set to 0. List the binary values in register A and carry flipflop after each shift.
The serial adder of the figure uses 4-bit registers. Register A holds binary number 0101 and register B holds 0111. The carry flip-flop is initially set to 0. List the b...
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Apr 6, 2019
Digital Logic
digital-logic
morris-mano
sequential-circuit
registers
serial-adder
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659
Morris Mano Edition 3 Exercise 7 Question 9 (Page No. 303)
Draw the logic diagram of a 4-bit register with four D flip-flops and four $4 \times 1$ multiplexer with mode-selection inputs $s _1 and s _0$. The register operates according to the following function table: $s _1$ ... no change 0 1 complement the four output 1 0 clear register to 0 (synchronous with the clock) 1 1 load parallel data
Draw the logic diagram of a 4-bit register with four D flip-flops and four $4 \times 1$ multiplexer with mode-selection inputs $s _1 and s _0$. The register operates acco...
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339
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Apr 6, 2019
Digital Logic
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660
Morris Mano Edition 3 Exercise 7 Question 8 (Page No. 303)
Design a shift register with a parallel load that operates according to the following function table: shift load register operation 0 0 no change 0 1 load parallel data 1 x shift right
Design a shift register with a parallel load that operates according to the following function table:shiftloadregister operation00no change01load parallel data1xshift rig...
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425
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Apr 6, 2019
Digital Logic
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