Recent questions tagged effective-memory-access

0 0 votes
1 1 answer
161
161 views
A machine uses a two-level page table. The page-directory base address is held in a register.Assume:One physical-memory access takes $100$ ns Page directories and page ta...
1 1 vote
1 1 answer
131
131 views
A paged virtual-memory system has the following measured parameters:\[\begin{array}{|l|l|}\hline\textbf{Measurement} & \textbf{Value} \\\hlineP_t = \text{probability of a...
1 1 vote
1 1 answer
93
93 views
Which of the following statements about small $(4 ~\text{KB})$ and large $(4 ~\text{MB})$ pages are correct?Large pages allow for a more efficient use of the TLB. Accessi...
1 1 vote
1 1 answer
86
86 views
Consider a three level paging scheme with a TLB. Assume no page fault occurs. It takes $1 ~\text{ns}$ to search the TLB and $100 ~\text{ns}$ to access the physical memory...
2 2 votes
3 answers 3 answers
404
404 views
0 0 votes
1 1 answer
300
300 views
The average time required to search a storage location in memory and obtain its contents is called :Access timeLatency timeResponse timeReading time
0 0 votes
1 answers 1 answer
336
336 views
C10. You are given a processor having a single-level cache hierarchy with only an \(L_1\) cache that has a \(95%\) hit rate. You have tore-design the cache hierarchy with...
0 0 votes
2 answers 2 answers
379
379 views
Consider a computer with two-level cache system $L_{1}$ and $L_{2}$ along with a main memory $M$. The $L_{1}$ cache is divided into two parts: I-cache (Instruction cache)...
0 0 votes
1 1 answer
467
467 views
If a page of a process is in secondary memory but not in main memory then what should be it's page table entry.Then how logical address is converted to physical address.W...
1 1 vote
2 2 answers
1.3k
1.3k views
Consider a 5–stage pipelined processor with stages – Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MA) and Write Back (WB). All stages exc...
0 0 votes
1 1 answer
1.4k
1.4k views
Assuming 3-level of paging is used by a paging system and a TLB for address translation. Calculate Average memory access time if each main memory access takes 100ns and T...
1 1 vote
1 1 answer
921
921 views
The access time of a main memory is 800 ns and cache memory access time is 70 ns. The ratio of read and write requests is 7:3. The hit ratio for read access only is 80%. ...
0 0 votes
1 1 answer
598
598 views
Given values:1-level page tableMemory access time =10msPage fault service time=20ms Page fault rate=40% what is the effective memory access time?
0 0 votes
0 0 answers
393
393 views
which one is correct to use in exam here (1-p) is as page faultEMAT=p(m+m)+(1-p)(pfst)https://gateoverflow.in/333178/gate-cse-2020-question-53this is a tlb question but m...
0 0 votes
1 1 answer
573
573 views
2 2 votes
1 1 answer
5.2k
5.2k views
A demand paging system provides a TLB (15 ns access time), cache memory (25 ns access time), main memory (75 ns access time, NOT including the cache “miss”) and 5 ms to s...
1 1 vote
0 0 answers
541
541 views
0 0 votes
1 1 answer
385
385 views
Could you please differentiate below. Memory access time.hit time. search time??Arey yar some one answer this.. why so dumb
0 0 votes
1 answers 1 answer
6.3k
6.3k views
Consider a machine with $40 \; \text{MHz}$ processor which has run a benchmark program. The executed program consists of $100,000$ instruction executions, with the follow...
0 0 votes
0 0 answers
467
467 views
When a cache is $10 \; \text{times}$ faster than main memory, and the cache can be used $70 \%$ of the time, how much speed can be gained using cache $?$$\simeq 10$$\sime...
3 3 votes
1 answers 1 answer
1.0k
1.0k views
Consider a two-level memory hierarchy with separate instruction and data caches in level 1, and main memory in level 2. The clock cycle time in 1 ns. The miss penalty is ...
2 2 votes
1 answers 1 answer
550
550 views
Assume that a read request takes 50 nsec on a cache miss and 5 nsec on a cache hit. While running a program, it is observed that 80% of the processor’s read requests resu...
2 2 votes
2 answers 2 answers
874
874 views
Consider the following memories with their miss rates and hit times Then the average memory access time is ______ (in ns)\begin{tabular}{|l|l|l|}\hline Hardware & Miss Ra...