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Recent questions tagged effective-memory-access
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GO Classes DPP | GATE CS | Operating System | Effective Access Time
A machine uses a two-level page table. The page-directory base address is held in a register.Assume:One physical-memory access takes $100$ ns Page directories and page ta...
GO Classes
161
views
asked
Aug 14
Operating System
goclasses
goclasses-cs-dpp
operating-system
goclasses-cs-dpp-day-348
goclasses-os-practice-questions
effective-memory-access
page-faults
translation-lookaside-buffer
numerical-answers
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1
1 vote
1
1 answer
131
131 views
GO Classes DPP | GATE CS | Operating System | Effective Access Time
A paged virtual-memory system has the following measured parameters:\[\begin{array}{|l|l|}\hline\textbf{Measurement} & \textbf{Value} \\\hlineP_t = \text{probability of a...
GO Classes
131
views
asked
Aug 13
Operating System
goclasses
goclasses-cs-dpp
operating-system
goclasses-cs-dpp-day-347
goclasses-os-practice-questions
dirty-page
translation-lookaside-buffer
page-faults
effective-memory-access
numerical-answers
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1 vote
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93
93 views
GO Classes DPP | GATE CS | Operating System | Page Size and TLB
Which of the following statements about small $(4 ~\text{KB})$ and large $(4 ~\text{MB})$ pages are correct?Large pages allow for a more efficient use of the TLB. Accessi...
GO Classes
93
views
asked
Aug 10
Operating System
goclasses
goclasses-cs-dpp
operating-system
goclasses-cs-dpp-day-342
goclasses-os-practice-questions
effective-memory-access
page-size
multiple-selects
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1
1 vote
1
1 answer
86
86 views
GO Classes DPP | GATE CS | Operating System | TLB Access Time
Consider a three level paging scheme with a TLB. Assume no page fault occurs. It takes $1 ~\text{ns}$ to search the TLB and $100 ~\text{ns}$ to access the physical memory...
GO Classes
86
views
asked
Aug 10
Operating System
goclasses
goclasses-cs-dpp
operating-system
goclasses-cs-dpp-day-342
goclasses-os-practice-questions
effective-memory-access
translation-lookaside-buffer
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2
2 votes
3
answers
3 answers
404
404 views
Test ques.
js__
404
views
asked
Nov 5, 2025
CO & Architecture
co-and-architecture
cache-memory
effective-memory-access
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300
300 views
UGC NET CSE | December 2023 | Part 2 | Question: 29
The average time required to search a storage location in memory and obtain its contents is called :Access timeLatency timeResponse timeReading time
Shubham Sharma 2
300
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asked
Sep 9, 2025
Computer Peripherals
ugcnetcse-dec2023
co-and-architecture
memory-management
effective-memory-access
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5 votes
1
1 answer
909
909 views
MADE EASY TOPIC WISE TEST-13 PART SYLLABUS GATE CS 2026 OPERATING SYSTEM-1
A) 147 nsB) 130 nsC) 129 nsD) 124 ns
Ekalavyaa
909
views
asked
Jul 17, 2025
Operating System
operating-system
paging
multilevel-paging
translation-lookaside-buffer
effective-memory-access
made-easy-test-series
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0
0 votes
1
answers
1 answer
336
336 views
ISI 2023 | PCB -CS | Question :10
C10. You are given a processor having a single-level cache hierarchy with only an \(L_1\) cache that has a \(95%\) hit rate. You have tore-design the cache hierarchy with...
ASHIS 1
336
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asked
Apr 13, 2025
CO & Architecture
descriptive
co-and-architecture
cache-memory
effective-memory-access
isi2023-pcb
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2
answers
2 answers
379
379 views
ISI2022 - MCS - PCB (CS) | Question: 11
Consider a computer with two-level cache system $L_{1}$ and $L_{2}$ along with a main memory $M$. The $L_{1}$ cache is divided into two parts: I-cache (Instruction cache)...
admin
379
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asked
Oct 18, 2024
CO & Architecture
isi2022-mcs-pcb-cs
cache-memory
probability
effective-memory-access
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0 votes
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1 answer
467
467 views
Paging/Mapping
If a page of a process is in secondary memory but not in main memory then what should be it's page table entry.Then how logical address is converted to physical address.W...
piyush6388
467
views
asked
Jun 26, 2024
Operating System
operating-system
paging
effective-memory-access
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1 vote
2
2 answers
1.3k
1.3k views
pipelining hazard
Consider a 5–stage pipelined processor with stages – Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MA) and Write Back (WB). All stages exc...
24aaaa23
1.3k
views
asked
Oct 3, 2023
Operating System
operating-system
pipelining
effective-memory-access
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0
0 votes
1
1 answer
1.4k
1.4k views
OPERATING SYSTEM
Assuming 3-level of paging is used by a paging system and a TLB for address translation. Calculate Average memory access time if each main memory access takes 100ns and T...
24aaaa23
1.4k
views
asked
Oct 2, 2023
Operating System
operating-system
paging
effective-memory-access
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1
1 vote
1
1 answer
921
921 views
Topic: Hit Ratio
The access time of a main memory is 800 ns and cache memory access time is 70 ns. The ratio of read and write requests is 7:3. The hit ratio for read access only is 80%. ...
rahulkarmakar
921
views
asked
Jun 16, 2023
CO & Architecture
co-and-architecture
effective-memory-access
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0
0 votes
1
1 answer
598
598 views
#selfdoubt
Given values:1-level page tableMemory access time =10msPage fault service time=20ms Page fault rate=40% what is the effective memory access time?
Dknights
598
views
asked
Apr 25, 2023
Operating System
operating-system
effective-memory-access
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0
0 votes
0
0 answers
393
393 views
#self_doubt
which one is correct to use in exam here (1-p) is as page faultEMAT=p(m+m)+(1-p)(pfst)https://gateoverflow.in/333178/gate-cse-2020-question-53this is a tlb question but m...
Dknights
393
views
asked
Apr 16, 2023
Operating System
operating-system
effective-memory-access
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0
0 votes
1
1 answer
573
573 views
What is the solution?
I think the answer must be 500200ns
h4kr
573
views
asked
Dec 29, 2022
Operating System
operating-system
virtual-memory
probability
effective-memory-access
made-easy-test-series
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2
2 votes
1
1 answer
5.2k
5.2k views
Calculate the effective access time.
A demand paging system provides a TLB (15 ns access time), cache memory (25 ns access time), main memory (75 ns access time, NOT including the cache “miss”) and 5 ms to s...
hoangminh
5.2k
views
asked
Nov 30, 2022
Operating System
operating-system
effective-memory-access
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1
1 vote
0
0 answers
541
541 views
Madeasy Test series
vishnu777
541
views
asked
Nov 23, 2022
CO & Architecture
multilevel-cache
made-easy-test-series
effective-memory-access
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0
0 votes
1
1 answer
385
385 views
Accesing time
Could you please differentiate below. Memory access time.hit time. search time??Arey yar some one answer this.. why so dumb
Subbu.
385
views
asked
Aug 6, 2022
CO & Architecture
co-and-architecture
effective-memory-access
hit-ratio
self-doubt
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0
0 votes
1
answers
1 answer
6.3k
6.3k views
NIELIT 2022 April Scientist B | Section B | Question: 102
Consider a machine with $40 \; \text{MHz}$ processor which has run a benchmark program. The executed program consists of $100,000$ instruction executions, with the follow...
soujanyareddy13
6.3k
views
asked
Apr 12, 2022
Others
nielit2022apr-scientistb
co-and-architecture
effective-memory-access
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0
0 votes
0
0 answers
467
467 views
NIELIT 2021 Dec Scientist B - Section B: 113
When a cache is $10 \; \text{times}$ faster than main memory, and the cache can be used $70 \%$ of the time, how much speed can be gained using cache $?$$\simeq 10$$\sime...
soujanyareddy13
467
views
asked
Dec 7, 2021
Others
nielit2021dec-scientistb
cache-memory
effective-memory-access
co-and-architecture
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3
3 votes
1
answers
1 answer
1.0k
1.0k views
NPTEL Assignment
Consider a two-level memory hierarchy with separate instruction and data caches in level 1, and main memory in level 2. The clock cycle time in 1 ns. The miss penalty is ...
LRU
1.0k
views
asked
Dec 4, 2021
CO & Architecture
nptel-quiz
co-and-architecture
effective-memory-access
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2
2 votes
1
answers
1 answer
550
550 views
NPTEL Assignment
Assume that a read request takes 50 nsec on a cache miss and 5 nsec on a cache hit. While running a program, it is observed that 80% of the processor’s read requests resu...
LRU
550
views
asked
Dec 4, 2021
CO & Architecture
nptel-quiz
co-and-architecture
effective-memory-access
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2
2 votes
2
answers
2 answers
874
874 views
Applied Test Series
Consider the following memories with their miss rates and hit times Then the average memory access time is ______ (in ns)\begin{tabular}{|l|l|l|}\hline Hardware & Miss Ra...
LRU
874
views
asked
Nov 5, 2021
CO & Architecture
test-series
co-and-architecture
cache-memory
effective-memory-access
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