Recent questions tagged sequential-circuit

4 4 votes
1 1 answer
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Consider the following circuit :If $A n, B n$ denote the next state corresponding to current states $A, B$ respectively, thenFor this circuit, which of the following is/a...
4 4 votes
1 1 answer
625
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Consider the sequential circuit shown in the figure, where both flip-flops “$\text{FD A}$” and “$\text{FD B}$” used are positive edge-triggered $D$ flip-flops. The state ...
3 3 votes
1 1 answer
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Consider the sequential circuit shown in the figure, where both flip-flops “$\text{FD A}$” and “$\text{FD B}$” used are positive edge-triggered $D$ flip-flops. The state ...
4 4 votes
1 1 answer
488
488 views
Consider the following circuit.What are the values of $P, Q, R$ after two cycles if $P=0, Q=1$ and $R=0$ to begin with?$011$$101$$100$$111$
4 4 votes
1 1 answer
817
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Consider the following circuit.$10011000010$ is supplied to the "data" terminal in $11$ clock cycles. After that the values of $q_2 q_1 q_0$ are$000$$010$$101$$111$
1 1 vote
0 0 answers
663
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Consider a combination of $\text{T}$ and $\text{D}$ flip-flops connected as shown below. The output of the $\text{D}$ flipflop is connected to the input of the $\text{T}$...
30 30 votes
6 answers 6 answers
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Consider a $3$-bit counter, designed using $T$ flip-flops, as shown below:Assuming the initial state of the counter given by $\text{PQR}$ as $000$, what are the next thre...
2 2 votes
1 1 answer
888
888 views
Which flip-flop is used to make all types of shift registers?JK flip-flopD flip-flopT flip-flopAll the options
1 1 vote
4 4 answers
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A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip-flops having a propagation delay of $10$ ns each. If the worst case delay in the ripple cou...
0 0 votes
3 3 answers
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A sequential circuit using D flip-flop and logic gates is shown in Figure, where $X$ and $Y$ are the inputs and $Z$ is the output. The circuit is$\text{S-R}$ Flip-flop wi...
1 1 vote
2 2 answers
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A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip-flops having a propagation delay of $10$ ns each. If the worst case delay in the ripple cou...
2 2 votes
1 1 answer
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A sequential circuit outputs a $\text{ONE}$ when an even number$(>0)$ of one’s are input; otherwise the output is $\text{ZERO}.$ The minimum number of states required is$...
2 2 votes
3 3 answers
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If a clock with time period $“T”$ is used with $n$ stage shift register, then output of final stage will be delayed by$nT$ sec$(n-1)T$ sec$n/T$ sec$(2n-1)T$ sec
0 0 votes
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In a ripple counter using edge-triggered $JK$ flip-flops, the pulse input is applied toClock input of all flip-flops$J$ and $K$ input of one flip-flop$J$ and $K$ input of...
2 2 votes
4 answers 4 answers
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The number of columns in a state table for a sequential circuit with $’m’$ flip flops and $’n’$ input is$m+n$$m+2n$$2m+n$$2m+2n$
1 1 vote
2 2 answers
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In a ripple counter using edge-triggered $JK$ flip-flops, the pulse input is applied toClock input of all flip-flops$J$ and $K$ input of one flip-flop$J$ and $K$ input of...
3 3 votes
2 2 answers
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The output of a sequential circuit depends on present inputs onlypast inputs onlyboth present and past inputspresent outputs only
3 3 votes
1 1 answer
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In a ripple counter using edge triggered $JK$ flip-flops, the pulse input is applied to theclock input of all flip-flopsclock input of one flip-flop$J$ and $K$ inputs of ...
3 3 votes
2 2 answers
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What will be the final output of D flip-Flop if the input string is $0010011100$?$1$$0$Don’t CareNone of the above
2 2 votes
1 1 answer
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What will be the final output of D Flip-Flop, if the input string is $11010011$?$1$$0$Don’t CareNone of the above
0 0 votes
1 1 answer
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Essential hazards may occur in :Combinational logic circuitsSynchronous sequential logic circuitsAsynchronous sequential logic circuits working in the fundamental modeAsy...
9 9 votes
1 1 answer
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A new flipflop with inputs $X$ and $Y$, has the following property$$\begin{array}{|c|c|c|}\hline \bf{X}& \bf{Y}& \bf{Current\ state}&\bf{ Next\ state} \\\hline 0&0&Q&...
0 0 votes
0 0 answers
932
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The boolean functions for the input of SR latch are as follows. Obtain the circuit diagram using a minimum number of NAND gates.$S = x _1’x _2’x _3 + x _1x _2x _3$.$R = x...
3 3 votes
0 0 answers
988
988 views
Draw the logic diagram of the product of sum expression$ Y = (x _1 + x _2’)(x _2 + x _3)$Show that there is a static 0 hazard when $x _1$ and $x _3$ is equal to zero and...