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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2024-1} & \textbf{2024-2} & \textbf{2023} &  \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 2&2&2& 3 &1&2&1&2&3
\\\hline\textbf{2 Marks Count} & 3&3&4& 2 &2&2&2&2.67&4
\\\hline\textbf{Total Marks} & 8&8&10& 7 &5&6&\bf{5}&\bf{7.33}&\bf{10}\\\hline
\end{array}}}$$

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COA : Control Unit
Design a vertical micro programmed control unit to generate 40 signals. Out of first 35 those only 3 signals can be active at a time. And remaining 5, ... the control memory required is? I am not able to solve this question please help
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Data Representation and Arithmetic Algorithms
MULTIPLICATION OF (-15) AND (3) USING BOOTH'S ALGORITHMPlease solve this question😭
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BARC 2024 CSE
How many 256 X 1K bit chips are required to build 1 MB of memory?
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Made Easy Class Question.
Consider the 4-stages(S1, S2, S3, S4) pipeline where different instructions are spending different cycles at different stages given below.S1S2S3S4I11312I21131I32112I41112 ... the instruction "I2" will be available after _____ cycles for I2.
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GATE CSE 2024 | Set 2 | Question: 1
Consider a computer with a $4 \mathrm{MHz}$ processor. Its $\text{DMA}$ controller can transfer $8$ bytes in $1$ cycle from a device to main memory through cycle stealing ... $?$2,56,000$3,200$25,60,000$32,000$
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GATE CSE 2024 | Set 2 | Question: 21
An instruction format has the following structure:Instruction Number: Opcode destination reg, source reg-$1$, source reg-$2$ Consider the following sequence of instructions to be ... $\text{I 3}$ and $\text{I 4}$
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GATE CSE 2024 | Set 2 | Question: 47
A processor with $16$ general purpose registers uses a $32$-bit instruction format. The instruction format consists of an opcode field, an addressing ... maximum number of unique opcodes possible for every addressing mode is ___________.
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GATE CSE 2024 | Set 2 | Question: 48
A non-pipelined instruction execution unit operating at $2 \mathrm{GHz}$ takes an average of $6$ ... place) obtained by the pipelined design over the non-pipelined design is ____________.
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GATE CSE 2024 | Set 2 | Question: 51
A processor uses a $32$-bit instruction format and supports byte-addressable memory access. The $\text{ISA}$ of the processor has $150$ distinct instructions. The ... value/address field. The value of $\text{X+2Y+Z}$ is __________.
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GATE CSE 2024 | Set 1 | Question: 5
Which one of the following statements is FALSE?In the cycle stealing mode of DMA, one word of data is transferred between an I/ ... executing an interrupt service routine faster with vectored interrupts than with non-vectored interrupts
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GATE CSE 2024 | Set 1 | Question: 20
Consider a $5$-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback ... does not require any extra hardware to retrieve the data from the pipeline stages
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GATE CSE 2024 | Set 1 | Question: 43
Consider two set-associative cache memory architectures: $\text{WBC}$, which uses the write back policy, and $\text{WTC}$, which uses the write ... the victim cache block to main memory before loading the missed block to the cache
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GATE CSE 2024 | Set 1 | Question: 45
The baseline execution time of a program on a $2 \mathrm{GHz}$ single core machine is $100$ nanoseconds ( $n s)$ ... of time.The number of cores that minimize the execution time of the program is __________.
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GATE CSE 2024 | Set 1 | Question: 46
A given program has $25 \%$ load/store instructions. Suppose the ideal $\text{CPI}$ (cycles per instruction) without any memory stalls is $2$. The program ... a perfect cache (i.e., with NO data or instruction cache misses) is __________.
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4 votes
GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 55
Consider the cache of size 512 bytes that is direct-mapped?Suppose the size of integer is 4 bytes and block size is 16 bytes. Assume cache is initially empty ... }What is the miss rate for the above loop? (roundoff to two decimal places)
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GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 62
At a particular point in time, the buffer cache has dirty data that needs to be flushed to disk. Suppose that the identities of these blocks can ... (initially moving upwards)Look (initially moving upwards)C-SCAN (initially moving upwards)
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906
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11 votes
GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 63
Assume an instruction mix of $15 \%$ conditional branches, $1 \%$ unconditional branches, $84 \%$ all others, and $60 \%$ of the conditional branches are ... both "predict taken", "predict not taken" branch predictions, CPI is the $1.30$
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#pipeline#coa#mocktest
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GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 34
In typical RISC ISA, delayed branch executes which instruction irrespective of whether the branch condition is true or false?Instruction immediately following ... to a different a subroutineIt waits till the branch condition is evaluated
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9 votes
GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 53
Suppose we use $\textsf{IEEE-754}$ single precision floating point format to represent the numbers in binary. What will be the hexadecimal representation ... $\textsf{0x80000008}$\textsf{0x80000010}$\textsf{0x80000002}$
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6 votes
GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 54
Assume a cache memory with the following properties:The cache size $\text{(C)}$ is 512 bytes (contains $512$ data bytes)The cache uses an LRU (least recently used) policy ... $\text{B}=8$ bytes$\text{B}=16$ bytesNone of the above.
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5 votes
GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 58
Your code is required to perform the function $(\text{M}\%16) \ast 3.$ What should you do to eliminate multiplication ($\ast$) and mod($\%$ ... the result, shift result left by $2,$ and add the saved result to current result.
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595
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3 answers
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MADE EASY TEST SERIES 2024 #COA
Consider 16 bit CPU with 4 GB RAM supports 2 Address Instruction with Address 1 uses direct addressing mode Address2 uses indirect addressing mode. Opcode is ... consumes 6 cycles. Time required to complete the instruction is in (ns).
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GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 5
Suppose we have a four-way set associative physically addressed cache of size $256 \mathrm{KB}$ and $\text{16B}$ blocks, on a machine that uses $32$-bit physical addresses. How many bits will be used for the index?
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6 votes
GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 20
The clock rate for Machine $\mathrm{A}$ is $2.4 \mathrm{GHz}$, and the clock rate for machine $\text{B}$ is $3.0 \mathrm{GHz}$. For a particular program, the average ... , with respect to this program. What is $\mathrm{K}?$1$4 / 3$2$3 / 4$
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754
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3 answers
7 votes
GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 48
Consider a processor with a branch-if-equal instruction that is $32$ bits long$\textsf{: BEQ R12, R11, X.}$ $6$ bits are used to encode the opcode, ... away (the number of instructions) from the $\textsf{BEQ}$ instruction could we reach?
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GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 49
Consider the following code fragment:Identify all data dependencies (potential data hazards) in the given code snippet within one loop iteration. Let the number of true data dependencies ... .What is $\mathrm{X}+2 \mathrm{Y}+3 \mathrm{Z}?$
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GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 50
A computer has a $32$-bit address bus with a direct mapped cache, using $4$ bits for block offset, $16$ tag bits, and $12$ index bits.Which of the following address ... $\textsf{2233 445 5}$ and $\textsf{2233 445 C}$
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computer architecture
a computer has 32-bit instructions and 12-bit addressing if there are already 250 two address instruction how many one address instruction can be formulated
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