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Recent questions tagged dma
5
votes
1
answer
31
MadeEasy Test Series: CO & Architecture - Dma
A hard disk with a transfer rate of 1 KBps is constantly transferring data to memory using DMA cycle stealing mode. The size of the data transfer is 16 bytes. The processor runs at 400 kHz clock frequency. The DMA controller requires ... time as 0.9375 sec and percentage time CPU gets blocked = transfer time/preparation time (IN case of cycle stealing)
A hard disk with a transfer rate of 1 KBps is constantly transferring data to memory using DMA cycle stealing mode. The size of the data transfer is 16 bytes. The process...
Shivam Kasat
2.5k
views
Shivam Kasat
asked
Dec 28, 2018
CO and Architecture
made-easy-test-series
co-and-architecture
dma
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0
votes
0
answers
32
william stallings I/O
a system employing interrupt-driven I/O for a particular device that transfers data at an average of 8 KB/s on a continuous basis. a. Assume that interrupt processing takes about 100 s (i.e., the time to jump to the interrupt service routine (ISR), ... getting 216/500 and 188/500 respectively. please check it. (i've taken K=1000 instead of 1024 for simplicity of calculation).
a system employing interrupt-driven I/O for a particular device that transfersdata at an average of 8 KB/s on a continuous basis.a. Assume that interrupt processing takes...
aambazinga
1.1k
views
aambazinga
asked
Dec 9, 2018
CO and Architecture
co-and-architecture
dma
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–
0
votes
1
answer
33
DMA cycle stealing
Consider a device with 1MB per second transfer rate and operating in cycle stealing mode of DMA. It requires 0.5 microsecond to transfer the data (1 byte) when it is ready or prepared. Percentage of CPU blocked due to DMA?
Consider a device with 1MB per second transfer rate and operating in cycle stealing mode of DMA. It requires 0.5 microsecond to transfer the data (1 byte) when it is read...
Ajit J
1.3k
views
Ajit J
asked
Dec 9, 2018
CO and Architecture
co-and-architecture
dma
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–
2
votes
0
answers
34
DMA Doubt
can someone explain what is preparation time in DMA exactly? and why is it multiplied by CPU cycle time in most of the questions here? does preparation time means that a word is brought into disk controller buffer from hard disk and it utilizes CPU? PS-DMA is giving me headaches!!!
can someone explain what is preparation time in DMA exactly?and why is it multiplied by CPU cycle time in most of the questions here?does preparation time means that a wo...
aditi19
606
views
aditi19
asked
Dec 8, 2018
CO and Architecture
dma
co-and-architecture
cycle
burst-mode
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–
0
votes
0
answers
35
Mode of data transfer
Which of the following mode of data transfer uses Interrupt mechanism ? (More then may be correct) Programmed I/O Interrupt Driven data transfer DMA Mode Asynchronous I/O Synchronous I/O None of the above
Which of the following mode of data transfer uses Interrupt mechanism ? (More then may be correct)Programmed I/OInterrupt Driven data transferDMA ModeAsynchronous I/OSync...
Na462
682
views
Na462
asked
Dec 8, 2018
CO and Architecture
co-and-architecture
dma
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–
0
votes
0
answers
36
DMA Cycle Stealing
A DMA controller uses the main memory buffer. It employs cycle stealing to deposit input data to this buffer. Suppose the external device uses a 9600 band transfer rate. Also, suppose the primary memory transfer rate is 100 million words/second with every 5th instruction cycle stolen. How long will it take to transfer 10K data from the external device to the buffer?
A DMA controller uses the main memory buffer. It employs cycle stealing to deposit input data to this buffer. Suppose the external device uses a 9600 band transfer rate. ...
Balaji Jegan
537
views
Balaji Jegan
asked
Dec 4, 2018
CO and Architecture
co-and-architecture
dma
numerical-answers
cycle-stealing
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–
2
votes
1
answer
37
MadeEasy Workbook: CO & Architecture - Dma
Consider a device of 1MBPS is operating in a cycle stealing mode of DMA .Whenever 16 B word is available it is transferred into memory in 4 microseconds. What is the % of time the processor is blocked due to DMA? a) 10% b) 20% c) 80% d) 90%
Consider a device of 1MBPS is operating in a cycle stealing mode of DMA .Whenever 16 B word is available it is transferred into memory in 4 microseconds. What is the % of...
Avir Singh
2.4k
views
Avir Singh
asked
Nov 20, 2018
CO and Architecture
co-and-architecture
dma
made-easy-booklet
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–
0
votes
1
answer
38
GRADE UP TEST SERIES
Consider a system in which DMA technique is used to transfer 16 MB of data from an I/O device into memory. The bandwidth of I/O device is 128 KB/s. The clock cycle of the CPU is 10 microseconds and word length of CPU is 32 bits. What percentage of time is the CPU in busy mode (upto 2 decimal place) ?
Consider a system in which DMA technique is used to transfer 16 MB of data from an I/O device into memory. The bandwidth of I/O device is 128 KB/s. The clock cycle of the...
ANIKET MANDRULKAR
246
views
ANIKET MANDRULKAR
asked
Oct 10, 2018
CO and Architecture
co-and-architecture
dma
numerical-answers
grade-up-test-series
+
–
2
votes
1
answer
39
#CO DMA modes and % of time CPU stays idle.
Consider y μs is cycle time / transfer time (for memory) x μs is data transfer time / preparation time (for disk) then % of time CPU idle in CYCLE STEALING MODE is = y/x and % of time CPU idle in Burst MODE is = (y)/(x+y) May someone please explain how is this Cpu idle time is calculated in both cycle stealing time and burst mode
Consider y μs is cycle time / transfer time (for memory) x μs is data transfer time / preparation time (for disk) then % of time CPU idle in CYCLE STEALING MODE is ...
iarnav
1.6k
views
iarnav
asked
Oct 5, 2018
CO and Architecture
co-and-architecture
dma
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–
0
votes
1
answer
40
general query
Can anyone suggest me best resource for IO organization, DMA and hard disk structure in CO. I am getting difficulty in these topics.
Can anyone suggest me best resource for IO organization, DMA and hard disk structure in CO. I am getting difficulty in these topics.
mb14
184
views
mb14
asked
Sep 19, 2018
CO and Architecture
co-and-architecture
io-organization
dma
disk
+
–
1
votes
0
answers
41
ISI2016-PCB-CS-2
Consider sending a large file of $360,000$ bits from Host $A$ to Host $B,$ connected through a router, as shown in the below figure $2.$ Assume that there is no queuing and propagation delay, and the router has sufficient buffer space. Host ... transferring one byte involves $4$ operations: in-status, check-status, branch and read/write in memory, each requiring one machine cycle.
Consider sending a large file of $360,000$ bits from Host $A$ to Host $B,$ connected through a router, as shown in the below figure $2.$ Assume that there is no queuing a...
go_editor
552
views
go_editor
asked
Sep 18, 2018
Computer Networks
isi2016-pcb-cs
link-state-routing
dma
non-gate
descriptive
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–
0
votes
1
answer
42
SELF DOUBT
https://gateoverflow.in/131079/coa-dma FOR BURST MODE IT SHOULD ALSO SYSTEM BUS??
https://gateoverflow.in/131079/coa-dmaFOR BURST MODE IT SHOULD ALSO SYSTEM BUS??
eyeamgj
322
views
eyeamgj
asked
Sep 13, 2018
CO and Architecture
co-and-architecture
dma
self-doubt
+
–
0
votes
2
answers
43
Computer Organisation
sidlewis
922
views
sidlewis
asked
Sep 12, 2018
CO and Architecture
co-and-architecture
dma
memory
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–
0
votes
0
answers
44
Self Doubt
Since a DMA contoller is connected with the number of I/O devices. Is it possible that DMA controller (say master) is connected with number of other DMA controllers (say slaves). And with these slaves DMA controller, a number of I/O devices are connected?
Since a DMA contoller is connected with the number of I/O devices. Is it possible that DMA controller (say master) is connected with number of other DMA controllers (say ...
!KARAN
236
views
!KARAN
asked
Sep 11, 2018
CO and Architecture
co-and-architecture
dma
self-doubt
+
–
0
votes
0
answers
45
Direct Memory Access
Locality of Reference is use Cache Memory but not DMA. Why? I mean atleast temporal locality should use DMA. as definition of temporal locaity is "Temporal locality refers to the reuse of specific data, and/or resources, within a relatively small time duration" So, it can use direct memory . right?
Locality of Reference is use Cache Memory but not DMA. Why?I mean atleast temporal locality should use DMA. as definition of temporal locaity is "Temporal locality refers...
srestha
660
views
srestha
asked
Jul 25, 2018
Operating System
dma
locality-of-reference
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–
0
votes
1
answer
46
DMA Transfer rate
Consider 8-bit DMA device operating in cycle stealing mode (Single Transfer Mode). Each DMA cycle takes 6 clock and each clock is of 2 MHz. An intermediate CPU machine cycle take 2 μsec. What is the data transfer rate of DMA? Ans. 200 KB/sec
Consider 8-bit DMA device operating in cycle stealing mode (Single Transfer Mode). Each DMA cycle takes 6 clock and each clock is of 2 MHz. An intermediate CPU machine cy...
Na462
1.1k
views
Na462
asked
Jul 23, 2018
CO and Architecture
co-and-architecture
dma
disk
+
–
0
votes
1
answer
47
DMA CPU consumed or blocked
In DMA, there are two modes of transferring data: burst and cycle stealing. Also, there are two states of CPU when operating DMA: either it's blocked or consumed. I want to know whether CPU is blocked or consumed when operating in burst mode, and same for cycle stealing mode.
In DMA, there are two modes of transferring data: burst and cycle stealing. Also, there are two states of CPU when operating DMA: either it's blocked or consumed.I want t...
habedo007
632
views
habedo007
asked
Jul 4, 2018
CO and Architecture
co-and-architecture
dma
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–
0
votes
0
answers
48
DMA Controller
DMA is mainly used to control faster processor activity. Then how processor time slows down by a DMA activity?
DMA is mainly used to control faster processor activity.Then how processor time slows down by a DMA activity?
srestha
506
views
srestha
asked
Jul 3, 2018
CO and Architecture
dma
co-and-architecture
+
–
0
votes
0
answers
49
ISI Mtech exam -2016
Please help me with this question.. The CPU of a system having an execution rate of 1 million instructions per second needs 4 machine cycles on an average for executing an instruction. On an average, 50% of the cycles use memory bus. For ... transferring one byte involves 4 operations: in-status, check-status, branch and read/write in memory, each requiring one machine cycle.
Please help me with this question..The CPU of a system having an execution rate of 1 million instructions per second needs 4 machine cycles on an average for executing an...
Vikram Saurabh
534
views
Vikram Saurabh
asked
May 3, 2018
CO and Architecture
userisi2016
usermod
dma
io-handling
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–
0
votes
2
answers
50
I/O organization- Hamacher
Consider a synchronous bus that operates according to the timing diagram in figure. The address transmitted by the processor appears on the bus after 4 ns. The propagation delay on the bus wires between the processor and different devices connected varies from 1 to ... . The input buffer needs 3 ns. set up time. What is maximum clock speed at which this bus can operate?
Consider a synchronous bus that operates according to the timing diagram in figure. The address transmitted by the processor appears on the bus after 4 ns. The propagatio...
srestha
2.4k
views
srestha
asked
Apr 8, 2018
CO and Architecture
co-and-architecture
dma
+
–
3
votes
0
answers
51
DMA Cycle Stealing Mode
In the last step shouldn't it be (Y/X) and not (Y/X+Y) since its Cycle Stealing mode?
In the last step shouldn't it be (Y/X) and not (Y/X+Y) since its Cycle Stealing mode?
vishal chugh
1.3k
views
vishal chugh
asked
Jan 24, 2018
CO and Architecture
dma
co-and-architecture
+
–
1
votes
1
answer
52
Ace Test Series: CO & Architecture - DMA And Bus Architecture
Answer is D please explain
Answer is Dplease explain
ashish pal
556
views
ashish pal
asked
Jan 20, 2018
CO and Architecture
ace-test-series
co-and-architecture
dma
+
–
2
votes
1
answer
53
DMA Controller
vishal chugh
1.1k
views
vishal chugh
asked
Jan 15, 2018
CO and Architecture
dma
co-and-architecture
+
–
5
votes
1
answer
54
DMA Self Doubt
A device has been used in DMA. A word of 4 bytes can be transferred when it is available. The memory cycle time is 40 ms and CPU is idle for 10% of its time. What is the data transfer rate of the device for Burst mode and Cycle stealing mode. I'm getting Burst mode - 11.11 B/s Cycle stealing - 10 B/s Is it correct??
A device has been used in DMA. A word of 4 bytes can be transferred when it is available. The memory cycle time is 40 ms and CPU is idle for 10% of its time. What is the ...
Ashwin Kulkarni
1.7k
views
Ashwin Kulkarni
asked
Jan 9, 2018
CO and Architecture
dma
cycle-stealing
burst-mode
co-and-architecture
+
–
1
votes
1
answer
55
DMA - Data Transfer Rate
A computer consists of a CPU and an I/O device D connected to main memory M via a shared bus with a data bus width of one word (16-bits). The CPU can execute a maximum of 106 instructions per second. An average instruction requires six processor cycles, three of which use the memory ... or status-checking time] ? (A) 2.15 x 106 (B) 3.15 x 106 (C) 1.15 x 106 (D) 4.15 x 106
A computer consists of a CPU and an I/O device D connected to main memory M via a shared bus with a data bus width of one word (16-bits). The CPU can execute a maximum of...
ankitgupta.1729
1.4k
views
ankitgupta.1729
asked
Dec 20, 2017
CO and Architecture
dma
co-and-architecture
+
–
0
votes
1
answer
56
#Theory Doubt #DMA
consider given statement Cycle stealing mode:- 1.time taken by I/O device to transfer 1 word is T1ns 2.CPU cycle time is T2ns then my question is:- Q. Is time taken by DMA to transfer 1 word would be T2ns(equal to cpu cycle time or depend on ....?) please explain DMA working...??
consider given statement Cycle stealing mode:-1.time taken by I/O device to transfer 1 word is T1ns2.CPU cycle time is T2nsthen my question is:-Q. Is time taken by DMA to...
hs_yadav
342
views
hs_yadav
asked
Dec 8, 2017
CO and Architecture
dma
+
–
1
votes
2
answers
57
DMA & IO
DMA interface unit eliminates the need to use CPU registers to transfers data from (a) MAR to MBR (b) MBR to MAR (c) I/O units to memory (d) Memory to I/O units
DMA interface unit eliminates the need to use CPU registers to transfers data from(a) MAR to MBR (b) MBR to MAR(c) I/O units to memory (d) Mem...
Sunil8860
3.1k
views
Sunil8860
asked
Aug 8, 2017
CO and Architecture
co-and-architecture
dma
+
–
18
votes
1
answer
58
% time of CPU blocked in DMA
Please Explain the formulae for % time of CPU blocked in both Cycle Stealing mode and Burst mode of DMA
Please Explain the formulae for % time of CPU blocked in both Cycle Stealing mode and Burst mode of DMA
ankitgupta.1729
8.2k
views
ankitgupta.1729
asked
Jul 29, 2017
CO and Architecture
co-and-architecture
dma
+
–
1
votes
1
answer
59
DMA %CPU blocked equation
% CPU blocked or consumed = (x/y) (in case of cycle stealing) where x= data preparation time and y= data transfer time.. I read questions and answers using this formula but i cant understand how this formula is formulated .. how we are ... ; data transfer time ' , CPU is blocked for a period equal 'data preparation time'? Please someone help me with equation
% CPU blocked or consumed = (x/y) (in case of cycle stealing)where x= data preparation time and y= data transfer time.. I read questions and answers using this formula ...
Satyajeet Singh
2.8k
views
Satyajeet Singh
asked
Jun 13, 2017
CO and Architecture
dma
co-and-architecture
+
–
1
votes
1
answer
60
[COA] DMA
In cycle stealing mode,the DMA gets control over ? 1. Data and address bus 2.Data and control bus 3.Address and control bus 4. None
In cycle stealing mode,the DMA gets control over ?1. Data and address bus2.Data and control bus3.Address and control bus4. None
rahul sharma 5
1.2k
views
rahul sharma 5
asked
May 27, 2017
CO and Architecture
co-and-architecture
dma
+
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