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Recent questions tagged dma

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Register data transfer
Registers R1 and R2 contain memory address and data to be written in that memory adress respectively. To execute the instruction that transfers content of R2 to memory ad...
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CPU blocked time in DMA
Consider a disk drive with 16 surfaces, 512 tracks / surface, 256 sectors / track, 8 KB / sector with a rotation speed of 3600 rpm. The disk is operated in cycle stealing...
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DMA-VG
Consider a hard disk which when requested to read a sector of 2048 bytes, first reads into its own local memory, and then uses DMA to transfer it to the main memory over ...
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DMA madeeasy
Here device transfer rate is 416.7 us and cpu executing an instruction in .5 us.So how to decide the clock cycle time, to calculate the fraction of cpu slows down?
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3 3 votes
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Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 23
A hard disk is connected to a $2$ GHz processor through a DMA controller which works in burst mode. The initial set up of a DMA transfer takes $1000$ clock cycles for the...
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Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 17
The fastest mode of data transfer is:Programmable I/OInterrupt I/ODMABoth A and B
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IIT m november 2016
A DMA needs 5 clock cycle to transfer 8 byte data.how many clock needed to transfer 1024 byte of data ,if burst transfer is not used
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29 29 votes
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Hamacher-DMA
The average seek time and rotational delay in a disk system are 6ms and 3ms, respectively. The rate of data transfer to or from the disk is 30 Mbytes/sec and all disk ac...
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2 2 votes
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DMA anc CPU idle time
Which of the following statements is / are true?A. In DMA approach CPU never gets idle for data transfer.B. In DMA approach, CPU becomes idle whenever DMA controller stea...
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COA Interface
What is this RS – 232 interface . Somebody please explain in easy words please
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1 1 vote
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DMA transfer time
Initialize the address register Initialize the count to 500 LOOP: Load a byte from device Store in memory at address given by address register Increment the address regis...
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15 15 votes
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DMA -cycle stealing
Consider a system in which bus cycle takes 100 ns. Transfer of bus control from processor to device or device to processor, takes 250 ns. One of the IO device has data tr...
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online test series
A DMA module is transferring characters to memory using cycle stealing mode, from a device which is transmitting at a rate of 19200 bps. The rate at which processor is fe...
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DMA CONTROLLER CYCLE STEALING
Please explain DMA cycle stealing mode with a timeline diagram.Does the DMA wait for 1 byte before aquiring the bus control and is this the same time when CPU utilizes th...
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Cycle Stealing(DMA)
In Cycle Stealing, does the DMA interrupt the processor everytime, or it uses the cycle while the processor remains unknown of the fact?
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UGC NET CSE | December 2015 | Part 3 | Question: 5
A DMA controller transfers 32-bit words to memory using cycle Stealing. The words are assembled from a device that transmits characters at a rate of 4800 characters per s...
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William Stalling Computer Organization I/O (DMA) question CYCLE stealing VS Burst Mode
Solution : Some one please explain with correct sequence of steps in each mode and a rough timing diagram.
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6 6 votes
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Madeeasy
Suppose DMA is employed in two modes1)Cycle Steaking Mode2)Burst ModeTransfer of bus control from CPU to I/O or I/O to CPU takes 300ns. Assume the system in which bus cyc...
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5 5 votes
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ISRO CSE 2011 | Question: 58
In DMA transfer scheme, the transfer scheme other than burst mode iscycle techniquestealing techniquecycle stealing techniquecycle bypass technique
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13 13 votes
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ISRO CSE 2011 | Question: 39
Two control signals in microprocessor which are related to Direct Memory Access (DMA) are$\textsf{INTR \& INTA}$$\textsf{RD \& WR}$$\textsf{S0 \& S1}$$\textsf{HOLD \& HLD...
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12 12 votes
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ISRO-2013-14
A processor is fetching instructions at the rate of $1$ MIPS. A DMA module is used to transfer characters to RAM from a device transmitting at $9600$ bps. How much time w...
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71 71 votes
8 answers 8 answers
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GATE CSE 2016 | Set 1 | Question: 31
The size of the data count register of a $\text{DMA}$ controller is $16\;\text{bits}$. The processor needs to transfer a file of $29,154$ kilobytes from disk to main memo...
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13 13 votes
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DMA operation
A) Consider $1$mbps hard-disk is interfaced to the processor in a cycle stealing mode of DMA whenever $64$ bytes of data is available in the buffer,then it is transferred...
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DAM cycle stealing
How cycle stealing maximize i/o rate
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A hard disk with transfer rate of 20 kbps is constantly transferring data to memory using DMA cycle stealing mode
A hard disk with transfer rate of 20 kbps is constantly transferring data to memory using DMA cycle stealing mode. The size of data transfer is 32 bytes. The processor ru...
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3 3 votes
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GATE2005
Consider a disk drive with the following specifications:16 surfaces, 512 tracks/surface, 512 sectors/track, 1 KB/sector, rotation speed 3000 rpm. The disk is operated in ...
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3 3 votes
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DMA Q2
The MegaGiga hard disk rotates at $10000$ rpm ($6$ ms/rot) with a seek time given by = $1+0.001$tmsec, where $t$ is the number of tracks the arm seeks. Assume a block siz...
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Direct memory access is used for high-speed I/O devices.
Direct memory access is used for high-speed I/O devices.Why this happens.what is co relation between speed of I/O and DMA transfer becoz anyway DMA is more efficient than...
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1 1 vote
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percentage of time of cpu blockage during dma transfer
Consider a disk drive with following specifications: 16 surfaces, 512 tracks/surface, 512 sectors/sector, 1KB/sector, rot. speed 3000rpm. The disk is operated in cycle st...
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4 4 votes
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what is the processor time
Consider the disk drive with the following specification $16$ surface. $1024$ tracks per surface. $1024$ sectors/track, $1$ KB /sector rotation speed is $3000$ $\text{rp...
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