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Recent questions tagged multilevel-cache
1
1 vote
1
1 answer
237
237 views
Interesting Question on Cache Memory, CPI
A processor has a base CPI of 1.2. Every instruction requires one instruction fetch, and 30% of instructions are loads and 10% are stores.The L1 cache miss rate (same for...
Ultra_Instinct_AM
237
views
asked
Jan 7
CO & Architecture
cache-memory
multilevel-cache
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0
0 votes
2
2 answers
342
342 views
finding Tavg in cache memory
can someone please tell me that when to use 1.h1(t1) + (1-h1)(t2)2.t1 + (1-h1)(t2)in finding Tavg
Pratik_sharma 2
342
views
asked
Oct 27, 2025
CO & Architecture
cache-memory
multilevel-cache
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26
26 votes
7
7 answers
12.8k
12.8k views
GATE CSE 2025 | Set 2 | Question: 45
Given a computing system with two levels of cache (L1 and L2) and a main memory. The first level (L1) cache access time is $1$ nanosecond (ns) and the "hit rate" for L1 c...
admin
12.8k
views
asked
Feb 27, 2025
CO & Architecture
gatecse2025-set2
co-and-architecture
cache-memory
average-memory-access-time
multilevel-cache
numerical-answers
two-marks
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33
33 votes
8
8 answers
19.5k
19.5k views
GATE CSE 2025 | Set 1 | Question: 43
A computer has a memory hierarchy consisting of two-level cache $\text{(L1}$ and $\text{L2)}$ and a main memory. If the processor needs to access data from memory, it fir...
Arjun
19.5k
views
asked
Feb 27, 2025
CO & Architecture
gatecse2025-set1
co-and-architecture
cache-memory
multilevel-cache
average-memory-access-time
numerical-answers
two-marks
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0
0 votes
1
1 answer
394
394 views
Multilevel Cache
Consider a system with hit ratio of a cache and main memory are 70% and 90% respectively cache memory access times is 60 ns. When miss in cache then 8 word block is trans...
Miracle124
394
views
asked
Oct 18, 2024
CO & Architecture
co-and-architecture
cache-memory
multilevel
multilevel-cache
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0
0 votes
1
1 answer
337
337 views
Caching systems
Many symmetric multi-processor systems have different levels of caches; one level is local to each processing core, and another level is shared among all processing cores...
Sandeep Rishi J B
337
views
asked
Jul 1, 2024
CO & Architecture
co-and-architecture
multilevel-cache
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0
0 votes
1
answers
1 answer
1.5k
1.5k views
Cache Mapping
In a 2 level hierarchy, the cache has an access time of 15 ns and the main memory has an access time of 110 ns, the hit rate of the cache is 90%. If the block size of the...
Mrityudoot
1.5k
views
asked
Jun 5, 2023
CO & Architecture
co-and-architecture
cache-memory
multilevel-cache
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0
0 votes
0
0 answers
1.1k
1.1k views
cache miss question
In $T_{Read Avg}$, shouldn’t it be $T_{Read Avg}$ = (10*0.9) + 0.1*(10+100), because it must be checking the cache in case of cache miss too, right?
h4kr
1.1k
views
asked
Dec 27, 2022
CO & Architecture
co-and-architecture
cache-memory
multilevel-cache
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2
2 votes
1
1 answer
724
724 views
L1 and L2 cache
I have few doubts regarding $ L1$ and $ L2 $ cacheConsider there is sequential access to L1 and L2 cache i.e L2 is accessed after L1 misses$\textup{Doubt 1:}$Suppose we w...
Chaitanya Kale
724
views
asked
Dec 12, 2022
CO & Architecture
multilevel-cache
co-and-architecture
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1
1 vote
0
0 answers
557
557 views
Madeasy Test series
vishnu777
557
views
asked
Nov 23, 2022
CO & Architecture
multilevel-cache
made-easy-test-series
effective-memory-access
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2
2 votes
1
1 answer
1.3k
1.3k views
NIELIT Scientific Assistant A 2020 November: 70
A computer has a single cache (off-chip) with a $3$ ns hit time and a $95\%$ hit rate. Main memory has a $50$ ns access time. If we add an on-chip cache with a $0.6$ ns h...
gatecse
1.3k
views
asked
Dec 9, 2020
CO & Architecture
nielit-sta-2020
cache-memory
multilevel-cache
co-and-architecture
effective-memory-access
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0
0 votes
0
0 answers
1.3k
1.3k views
Computer organisation cache
Why can't we have n-levels of cache ?
Priyansh Singh
1.3k
views
asked
Jan 27, 2019
CO & Architecture
cache-memory
co-and-architecture
multilevel-cache
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0
0 votes
1
1 answer
630
630 views
MadeEasy Test Series: CO & Architecture - Cache Memory
Consider the following statements:(i) Accessing of data in a column wise fashion maintains spatial locality only when the block size is equal to the total size of the ele...
Jay Bhutada 1
630
views
asked
Jan 9, 2019
CO & Architecture
made-easy-test-series
co-and-architecture
multilevel-cache
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0
0 votes
1
1 answer
464
464 views
UPPCL AE 2018:32
Which of the following statement is $\text{TRUE}$?Doubling the block size and halving the number of sets will reduce capacity missesThe last-level cache is designed for h...
admin
464
views
asked
Jan 5, 2019
CO & Architecture
uppcl2018
co-and-architecture
cache-memory
multilevel-cache
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0
0 votes
0
0 answers
842
842 views
CO madeeasy 2019 Multi level cache
please explain how hit ratio of L2 is taken as 0.5? instead of 0.9 as 10 misses are mentionedis it like as 20 misses at levle 1 out of which only 10 missed at level 2, so...
Markzuck
842
views
asked
Dec 21, 2018
CO & Architecture
co-and-architecture
multilevel-cache
hit-ratio
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0
0 votes
0
0 answers
1.6k
1.6k views
Calculating average access time in multi level cache
$h_1→L1$ hit ratio $h_2→L2$ hit ratio$C_1→ L1$ access time$C_2→ $Miss penalty to transfer information from L2 to L1$M→$ Miss penalty to transfer information from main mem...
Raj Singh 1
1.6k
views
asked
Dec 19, 2018
CO & Architecture
cache-memory
multilevel-cache
co-and-architecture
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0
0 votes
0
0 answers
1.2k
1.2k views
conceptual doubt
in case of hierarchical memory organization when there is a miss in cache , we need to bring the entire block from main memory to cache so in the formula-AMAT= H1*T1+(1-H...
sushmita
1.2k
views
asked
Dec 12, 2018
CO & Architecture
co-and-architecture
cache-memory
effective-memory-access
multilevel-cache
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0
0 votes
0
0 answers
494
494 views
cache
Consider a system with the average memory access time of a processor with one level (L1) cache is 2.8 clock cycles. If the required data is present in L1-cache it can be ...
Satbir
494
views
asked
Dec 6, 2018
CO & Architecture
co-and-architecture
cache-memory
multilevel-cache
average-memory-access-time
numerical-answers
+
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1
1 vote
1
answers
1 answer
1.7k
1.7k views
miss penalty
Effective address time for a cache comprising of L1 and L2 cache =9nshit ratio of L1 cache = 0.8 hit ratio of L2 cache = 0.9memory access time =100nsMiss penalty of L1 ca...
Gate Fever
1.7k
views
asked
Nov 28, 2018
CO & Architecture
co-and-architecture
multilevel-cache
effective-memory-access
numerical-answers
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0
0 votes
1
1 answer
2.3k
2.3k views
cache memory
Consider a two-level memory hierarchy, L1 (cache) has an accessing time of 5 ns and main memory has an accessing time of 100 ns. Writing or updating contents takes 20 ns...
Shivangi Parashar 2
2.3k
views
asked
Nov 25, 2018
CO & Architecture
co-and-architecture
cache-memory
multilevel-cache
numerical-answers
+
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0
0 votes
1
1 answer
2.4k
2.4k views
Cache Memory
consider two-level cache hierarchies with L1 and L2 cache. Programs refer to memory 1000 times out of which 40 misses are in the L1 cache and 10 misses are in the L2 cach...
Shivangi Parashar 2
2.4k
views
asked
Nov 25, 2018
CO & Architecture
co-and-architecture
cache-memory
multilevel-cache
numerical-answers
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0
0 votes
1
1 answer
547
547 views
Gate forum Exam
In two level cache first level cache minimizes cache miss ratio , second level minimizes cache hit ratio . Explain .
kunal goswami
547
views
asked
Nov 17, 2018
CO & Architecture
co-and-architecture
multilevel-cache
gateforum-test-series
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0
0 votes
0
0 answers
475
475 views
Self-doubt What events happen in Cache Access duration
What events happen when we say that a cache at level i is accessed? (I am able to use the cache formulas as given in textbooks and also most of the times, I arrive at the...
Harsh Kumar
475
views
asked
Sep 29, 2018
CO & Architecture
cache-memory
multilevel-cache
co-and-architecture
self-doubt
+
–
0
0 votes
0
0 answers
543
543 views
Load Back Cache
In the memory access time formula for the hierarchical cache - which is given as :$Emat = H1\times T1 + (1-H1)(H2\times (T1+T2) + (1-H2)\times (T1+T2+T3))$ (where Hi = Hi...
Harsh Kumar
543
views
asked
Sep 29, 2018
CO & Architecture
co-and-architecture
cache-memory
multilevel-cache
load-back-cache
general-topic-doubt
+
–
0
0 votes
0
0 answers
325
325 views
Testseries
Suppose that in 500 memory references there are 50 misses in the first level cache and 20 misses in the second level cache. Assume miss penalty from the L2 cache to memor...
Shiv Gaur
325
views
asked
Sep 13, 2018
CO & Architecture
co-and-architecture
multilevel-cache
stall
test-series
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1
1 vote
1
1 answer
1.1k
1.1k views
performance of cache memory
in cache performace i have confusion about where to use which formula likefor write through whether use H (tc) + (1-H) (tc+m) or H (tc) + (1-H) (m)and how to identify wh...
Rahul_Rathod_
1.1k
views
asked
Aug 6, 2018
CO & Architecture
cache-memory
co-and-architecture
multilevel-cache
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0
0 votes
0
0 answers
607
607 views
performance cache exercise help
First level data cache: Direct mapping , writeThrough/write allocate , 8kb data and lines of 8 bytes, miss rate= 17%First level instructions cache: Direct mapping,, 4kb d...
mauro5991
607
views
asked
Aug 2, 2018
CO & Architecture
virtual-memory
cache-memory
co-and-architecture
memory-management
multilevel-cache
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0
0 votes
0
0 answers
542
542 views
Cache Memory
Hi sir, i want to ask that how we'll come to know whether this is an independent memory organization or it is a hierarchical organization ? In case of hierarchical it's a...
Priyansh Singh
542
views
asked
Jul 2, 2018
CO & Architecture
cache-memory
multilevel-cache
co-and-architecture
effective-memory-access
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