Recent questions tagged cache-memory / GATE Overflow for GATE CSE

0 votes

2 answers

631

UGC NET CSE | June 2012 | Part 2 | Question: 32
Cached and interleaved memories are ways of speeding up memory access between CPU's and slower RAM. Which memory models are best suited (i.e. improves the performance most) for which programs ? Cached memory is best suited for small loops. Interleaved ... sequential code. I and II are true I and III are true IV and II are true IV and III are true

Cached and interleaved memories are ways of speeding up memory access between CPU’s and slower RAM. Which memory models are best suited (i.e. improves the performance m...

Sanjay Sharma

4.0k views

Sanjay Sharma asked May 7, 2016

8 votes

5 answers

632

ISRO-2013-16
How much speed do we gain by using the cache, when cache is used $80$% of the time? Assume cache is faster than main memory. $5.27$ $2.00$ $4.16$ $6.09$

How much speed do we gain by using the cache, when cache is used $80$% of the time? Assume cache is faster than main memory.$5.27$$2.00$$4.16$$6.09$

makhdoom ghaya

10.3k views

makhdoom ghaya asked Apr 26, 2016

35 votes

4 answers

633

GATE CSE 2006 | Question: 75
Consider two cache organizations. First one is $32$ $kB$ $2$-way set associative with $32$ $byte$ block size, the second is of same size but direct mapped. The size of an address is $32$ $bits$ in both cases . A $2$-to-$1$ multiplexer has latency of $0.6 ns$ while a $k-$ ... of direct mapped is $h_2$. The value of $h_2$ is: $2.4$ $ns$ $2.3$ $ns$ $1.8$ $ns$ $1.7$ $ns$

Consider two cache organizations. First one is $32$ $kB$ $2$-way set associative with $32$ $byte$ block size, the second is of same size but direct mapped. The size of an...

go_editor

11.4k views

go_editor asked Apr 24, 2016

35 votes

6 answers

634

GATE CSE 2006 | Question: 81
A CPU has a $32$ $KB$ direct mapped cache with $128$ byte-block size. Suppose $A$ is two dimensional array of size $512 \times512$ with elements that occupy $8-bytes$ each. Consider the following two $C$ code segments, $P1$ and $P2$. $P1$: for (i=0; i<512; i++) { for ( ... $M2$. The value of the ratio $\frac{M_{1}}{M_{2}}$: $0$ $\frac{1}{16}$ $\frac{1}{8}$ $16$

A CPU has a $32$ $KB$ direct mapped cache with $128$ byte-block size. Suppose $A$ is two dimensional array of size $512 \times512$ with elements that occupy $8-bytes$ eac...

go_editor

10.6k views

go_editor asked Apr 23, 2016

41 votes

5 answers

635

GATE CSE 2007 | Question: 81
Consider a machine with a byte addressable main memory of $2^{16}$ bytes. Assume that a direct mapped data cache consisting of $32$ lines of $64$ bytes each is used in the system. A $50$ x $50$ two-dimensional array of bytes is stored in the main memory starting from memory ... time? line $4$ to line $11$ line $4$ to line $12$ line $0$ to line $7$ line $0$ to line $8$

Consider a machine with a byte addressable main memory of $2^{16}$ bytes. Assume that a direct mapped data cache consisting of $32$ lines of $64$ bytes each is used in th...

go_editor

10.2k views

go_editor asked Apr 23, 2016

32 votes

6 answers

636

GATE CSE 2008 | Question: 73
Consider a machine with a $2$-way set associative data cache of size $64$ Kbytes and block size $16$ bytes. The cache is managed using $32$ bit virtual addresses and the page size is $4$ Kbytes. A program to be run on this machine begins as follows: double ARR[ ... to array $\text{ARR}$. The cache hit ratio for this initialization loop is: $0\%$ $25\%$ $50\%$ $75\%$

Consider a machine with a $2$-way set associative data cache of size $64$ Kbytes and block size $16$ bytes. The cache is managed using $32$ bit virtual addresses and the ...

go_editor

8.6k views

go_editor asked Apr 23, 2016

61 votes

6 answers

637

GATE CSE 2008 | Question: 72
Consider a machine with a $2$-way set associative data cache of size $64$ Kbytes and block size $16$ bytes. The cache is managed using $32$ bit virtual addresses and the page size is $4$ Kbytes. A program to be run on this machine begins as follows: double ARR[1024][1024]; int i, j; ... $\text{ARR[0][4]}$ $\text{ARR[4][0]}$ $\text{ARR[0][5]}$ $\text{ARR[5][0]}$

Consider a machine with a $2$-way set associative data cache of size $64$ Kbytes and block size $16$ bytes. The cache is managed using $32$ bit virtual addresses and the ...

go_editor

15.8k views

go_editor asked Apr 23, 2016

73 votes

8 answers

638

GATE CSE 2010 | Question: 49
A computer system has an $L1$ cache, an $L2$ cache, and a main memory unit connected as shown below. The block size in $L1$ cache is $4$ words. The block size in $L2$ cache is $16$ words. The memory access times are $2$ ... cache to $L1$ cache. What is the total time taken for these transfers? $222$ nanoseconds $888$ nanoseconds $902$ nanoseconds $968$ nanoseconds

A computer system has an $L1$ cache, an $L2$ cache, and a main memory unit connected as shown below. The block size in $L1$ cache is $4$ words. The block size in $L2$ cac...

go_editor

26.4k views

go_editor asked Apr 21, 2016

32 votes

4 answers

639

GATE CSE 2012 | Question: 55
A computer has a $256$-$\text{KByte}$, 4-way set associative, write back data cache with block size of $32$ $\text{Bytes}$. The processor sends $32$ $\text{bit}$ addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, ... tag directory is: $160$ $\text{Kbits}$ $136$ $\text{Kbits}$ $40$ $\text{Kbits}$ $32$ $\text{Kbits}$

A computer has a $256$-$\text{KByte}$, 4-way set associative, write back data cache with block size of $32$ $\text{Bytes}$. The processor sends $32$ $\text{bit}$ addresse...

go_editor

12.4k views

go_editor asked Apr 21, 2016

50 votes

4 answers

640

GATE CSE 2016 Set 2 | Question: 32
The width of the physical address on a machine is $40$ bits. The width of the tag field in a $512$ KB $8$-way set associative cache is ________ bits.

The width of the physical address on a machine is $40$ bits. The width of the tag field in a $512$ KB $8$-way set associative cache is ________ bits.

Akash Kanase

17.9k views

Akash Kanase asked Feb 12, 2016

63 votes

13 answers

641

GATE CSE 2016 Set 2 | Question: 50
A file system uses an in-memory cache to cache disk blocks. The miss rate of the cache is shown in the figure. The latency to read a block from the cache is $1$ ms and to read a block from the disk is $10$ ms. Assume that the cost ... in multiples of $10$ MB. The smallest cache size required to ensure an average read latency of less than $6$ ms is _________ MB.

A file system uses an in-memory cache to cache disk blocks. The miss rate of the cache is shown in the figure. The latency to read a block from the cache is $1$ ms and to...

Akash Kanase

15.2k views

Akash Kanase asked Feb 12, 2016

9 votes

3 answers

642

Average access time in cache memory along with hard disk
A system has cache main memory and disk for virtual memory. If referenced word in cache $30$ ns to access it. If it is not in cache $80$ ns to load it in cache and reference is started again. If the word not in memory then $22$ms to ... memory and $80$ ns from memory to cache and start again. Cache hit ratio is $0.8$ memory hit ratio is $0.9$

A system has cache main memory and disk for virtual memory. If referenced word in cache $30$ ns to access it. If it is not in cache $80$ ns to load it in cache and refere...

Pooja Palod

2.2k views

Pooja Palod asked Jan 31, 2016

2 votes

2 answers

643

cache
consider single level cache woth access time 5ns line size of 128 bytes and hit ratio is 0.97.Main memory uses block transfer capability that has first 8 bytes access time 50 ns and for remaining words 10ns What is access time when there is cache miss(Assume cache waits until line is fetched from memory and then reexecutes for hit)

consider single level cache woth access time 5ns line size of 128 bytes and hit ratio is 0.97.Main memory uses block transfer capability that has first 8 bytes access t...

Pooja Palod

781 views

Pooja Palod asked Jan 29, 2016

4 votes

1 answer

644

Set Associative Mapping
A byte addressable system with 16-bit address lines with a 2-way set associative, write back cache with perfect LRU replacement. Assume 1 valid bit and 1 dirty bit maintains for each block. The tag store requires a total of 4352 bits of storage. What is the block size of the cache? [in bytes]

A byte addressable system with 16-bit address lines with a 2-way set associative, write back cache with perfect LRU replacement. Assume 1 valid bit and 1 dirty bit mainta...

pC

2.2k views

pC asked Jan 28, 2016

1 votes

1 answer

645

average access time
the memory access time is 1 nanosecond for a read operation with a hit in cache, 5 nanoseconds for a read operation with a miss in cache, 2 nanoseconds for a write operation with a hit in cache and 10 nanoseconds for a write operation with a ... The cache hit-ratio is 0.9. The average memory access time (in nanoseconds) in executing the sequence of instructions is __________.

the memory access time is 1 nanosecond for a read operation with a hit in cache, 5 nanoseconds for a read operation with a miss in cache, 2 nanoseconds for a write operat...

apskumar

1.2k views

apskumar asked Jan 28, 2016

0 votes

2 answers

646

MadeEasy Test Series: CO & Architecture - Cache Memory
Suppose that in $250$ memory references, there are $30$ misses in first level cache and $10$ misses in second level cache. Assume that miss penalty from the L2 cache memory $50$ ... are $1.25$ memory references per instruction, then the average stall cycles per instruction is ________. answer given is $4$

Suppose that in $250$ memory references, there are $30$ misses in first level cache and $10$ misses in second level cache.Assume that miss penalty from the L2 cache memor...

sourav.

548 views

sourav. asked Jan 27, 2016

4 votes

2 answers

647

TLB ,VGATE
@Arjun sir, I solved it by using the same concept of gate 2003 78,79 ..but techtud marked it as wrong..this qs has only one confusion which is how to use page table walk and tlb update...I used it in the part of L3 ache miss of Tlb miss.. and used this formula . ... hit(cache time) + L2 miss( L3 hit (cache time) + L3 miss(cache time+page table walk and Tlb update )))) Sir,pls check this

@Arjun sir, I solved it by using the same concept of gate 2003 78,79 ..but techtud marked it as wrong..this qs has only one confusion which is how to use page table walk ...

resuscitate

1.3k views

resuscitate asked Jan 27, 2016

1 votes

1 answer

648

What is hit ratio? (including read and write)
In a system, integer has size of $4$ bytes. The system has $1024$ KB set associative cache with associativity $2$ and block size of $32$ bytes. Consider the program below. Assuming that initially A was not present in cache, cache hit ratio is ____ for(int i=0;i < 64;i++) { A[i] = A[i]+2; A[i+1] = A[i]+3; }

In a system, integer has size of $4$ bytes. The system has $1024$ KB set associative cache with associativity $2$ and block size of $32$ bytes. Consider the program below...

Avdhesh Singh Rana

883 views

Avdhesh Singh Rana asked Jan 24, 2016

0 votes

1 answer

649

MadeEasy Test Series: CO & Architecture - Cache Memory
getting 7/11

getting 7/11

Vertika Srivastava

375 views

Vertika Srivastava asked Jan 24, 2016

2 votes

2 answers

650

MadeEasy Test Series: CO & Architecture - Cache Memory
Consider the direct mapped cache organization which consists of m-lines with a line size of 2w words/ bytes. Main memory address can be viewed as consisting of three fields. The least significant w-bits identify a unique word within the block of main memory. ... answer would be 1,2,3, ... (m-1) but now i am confused what is asked in this ques.

Consider the direct mapped cache organization which consists of m-lines with a line size of 2w words/ bytes. Main memory address can be viewed as consisting of three fiel...

khushtak

1.1k views

khushtak asked Jan 21, 2016

1 votes

1 answer

651

Conflict Misses
Will conflict misses increase if k-way set associative cache is used and we increase the cache capacity?

Will conflict misses increase if k-way set associative cache is used and we increase the cache capacity?

Sumit1311

610 views

Sumit1311 asked Jan 21, 2016

0 votes

4 answers

652

MadeEasy Test Series: CO & Architecture - Cache Memory
Array A contains $256$ elements of $4$ bytes each. Its first element is stored at physical address $4,096.$ Array B contains $512$ elements of $4$ bytes each. Its first element is stored at physical address $8,192.$ Assume that only arrays A and B can ... to memory if the cache has a write-through policy? $a) 0$ $b) 256$ $c) 1,024$ $d) 2,048$

Array A contains $256$ elements of $4$ bytes each. Its first element is stored at physical address $4,096.$ Array B contains $512$ elements of $4$ bytes each. Its first e...

Sandeep Singh

2.7k views

Sandeep Singh asked Jan 19, 2016

1 votes

2 answers

653

MadeEasy Test Series: CO & Architecture - Cache Memory
Array A contains 256 elements of 4 bytes each. Its first element is stored at physical address 4,096. Array B contains 512 elements of 4 bytes each. Its first element is stored at physical address 8,192. Assume that only arrays A and B can ... many bytes will be written to memory if the cache has a write-through policy? a. 0 b 256 c 1024 d 2048

Array A contains 256 elements of 4 bytes each. Its first element is stored at physical address 4,096. Array B contains 512 elements of 4 bytes each. Its first element is ...

khushtak

601 views

khushtak asked Jan 18, 2016

1 votes

1 answer

654

Cache + VM
Q. are all these equal? Cache line size = Main memory block size = Virtual Memory Page size = Main memory Frame size? please clear the confusion between both these processes, whether they occur simultaneously or not and how?

Q. are all these equal?Cache line size = Main memory block size = Virtual Memory Page size = Main memory Frame size?please clear the confusion between both these process...

Aspi R Osa

389 views

Aspi R Osa asked Jan 16, 2016

0 votes

1 answer

655

TestBook Test Series: CO & Architecture - Cache Memory

Akash Kanase

593 views

Akash Kanase asked Jan 15, 2016

1 votes

0 answers

656

MadeEasy Test Series: CO & Architecture - Cache Memory
[MADEEASY] Consider a cache as follows : - Direct Mapped - 16 words total cache size - 4 words cache block size A sequence of 9 memory reads is performed in order from following addresses 2, 13, 6, 16, 11, 3, 10, 2, 13. What is maximum number of ... (in block 0) 13 => 011 | 01 - Hit (in block 3) Its giving (D) But answer is given as (C).

[MADEEASY]Consider a cache as follows :- Direct Mapped - 16 words total cache size - 4 words cache block sizeA sequence of 9 memory reads is performed in order fr...

Tushar Shinde

594 views

Tushar Shinde asked Jan 14, 2016

0 votes

2 answers

657

MadeEasy Test Series: CO & Architecture - Cache Memory
Assume that 16 bit cache address memory with cache size 1024 bytes. Block size of cache memory is 8 bytes and tag size is 9 bits. What is the associativity of cache memory? I am getting 8-way but answer is given as 4.

Assume that 16 bit cache address memory with cache size 1024 bytes. Block size of cache memory is 8 bytes and tag size is 9 bits. What is the associativity of cache memor...

Tushar Shinde

619 views

Tushar Shinde asked Jan 14, 2016

0 votes

1 answer

658

Ace Test Series: CO & Architecture - Cache Memory
I guess explaination is wrong. I am getting 216.

I guess explaination is wrong. I am getting 216.

Tushar Shinde

723 views

Tushar Shinde asked Jan 14, 2016

0 votes

1 answer

659

Virtual Gate Test Series: CO & Architecture - Cache Memory
Consider a $256k$ $4$- way set associative cache with block size $64$ Bytes. Main memory is $2Gb.$ The number of bits used for tag,set and word will be respectively? $10,15,6$ $9,16,6$ $8,17,6$ $7,18,6$ I think answer is $15,10,6 $ $\text{(tag,set,word)}$

Consider a $256k$ $4$- way set associative cache with block size $64$ Bytes. Main memory is $2Gb.$ The number of bits used for tag,set and word will be respectively?$10...

khushtak

468 views

khushtak asked Jan 13, 2016

0 votes

1 answer

660

LRU policy
In LRU policy for cache replacement. the least recently used block is replaced. So, what happens when all the slots are empty at beginning? Is LRU or MRU easier to implement? Why?

In LRU policy for cache replacement. the least recently used block is replaced. So, what happens when all the slots are empty at beginning?Is LRU or MRU easier to impleme...

Arjun

625 views

Arjun asked Jan 11, 2016

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