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Recent questions tagged machine-instruction

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4 Address Instruction
Where are 4 Address Instructions are used and how?
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How carry and zero flag bits are modified after CMP instruction is executed?
The instruction format is CMP R1, R2.How will the carry and zero flags we be modified after above instruction is executed? Case 1:R1< R2 Carry Flag = 1 Zero Flag = 0R1= R...
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GATE CSE 2021 | Set 1 | Question: 55
Consider the following instruction sequence where registers $\text{R1}, \text{R2}$ and $\text{R3}$ are general purpose and $\text{MEMORY[X]}$ denotes the content at the m...
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UGC NET CSE | October 2020 | Part 2 | Question: 75
Arrange the following types of machine in descending order of complexity.SISDMIMDSIMDChoose the correct answer from the options given below:$\text{i,ii,iii}$$\text{iii,ii...
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NIELIT 2016 MAR Scientist C - Section C: 45
An instruction used to set the carry flag in a computer can be classified asdata transferprocess controllogicalprogram control
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NIELIT 2017 OCT Scientific Assistant A (IT) - Section C: 8
Match list $I$ with List $II$ and select the correct answer using the codes given below the lists :$${\begin{array}{|c|c|c|}\hline&\textbf{List I} & & \textbf{List II}\\\...
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NIELIT 2017 OCT Scientific Assistant A (IT) - Section B: 35
In a $10$-bit computer instruction format, the size of address field is $3$-bits. The computer uses expanding OP code technique and has $4$ two-address instructions and $...
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NIELIT 2017 OCT Scientific Assistant A (CS) - Section B: 3
Match list $I$ with List $II$ and select the correct answer using the codes given below the lists.$${\begin{array}{|c|c|c|}\hline&\textbf{List I} & & \textbf{List II}\\\h...
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NIELIT 2016 DEC Scientist B (IT) - Section B: 39
MIMD stands forMultiple Instruction Multiple DataMultiple Instruction Memory DataMemory Instruction Multiple dataMultiple Information Memory data
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UGC NET CSE | January 2017 | Part 2 | Question: 32
Consider the following assembly language instructions:mov al, 15 mov ah, 15 xor al, al mov cl, 3 shr ax, cl add al, 90H add ah, 0What is the value in $ax$ register after ...
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UGC NET CSE | January 2017 | Part 2 | Question: 34
The contents of Register $(BL)$ and Register $(AL)$ of $8085$ microprocessor are $49H$ and $3AH$ respectively. The contents of $AL$, the status of carry flag $(CF)$ and s...
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GATE CSE 2020 | Question: 44
A processor has $64$ registers and uses $16$-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a re...
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ISRO CSE 2020 | Question: 16
A computer which issues instructions in order, has only $2$ registers and $3$ opcodes $\text{ADD, SUB}$ and $\text{MOV}$. Consider $2$ different implementations of the fo...
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Andrew S. Tanenbaum (OS) Edition 4 Exercise 2 Question 32 (Page No. 176)
Show how counting semaphores (i.e., semaphores that can hold an arbitrary value) can be implemented using only binary semaphores and ordinary machine instructions.
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Andrew S. Tanenbaum (OS) Edition 4 Exercise 1 Question 14 (Page No. 82)
A computer has a pipeline with four stages. Each stage takes the same time to do its work, namely, $1$ nsec. How many instructions per second can this machine execute?
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MadeEasy Test Series 2019: CO & Architecture - Machine Instruction
Q.A stack based CPU executes the instruction.Memory location 500 contains 0x88 and memory location 700 contains 0x37.The stack pointer is at 0x003F.The instructions are a...
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Self Doubt
Consider a hypothetical CPU which supports 2 address, 1 address and 0 address instructions. A 16 bit instruction is placed in 128 word memory. If there exists 2 two addre...
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Calculate number of times Zero Flag is Reset
I am getting 37.
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Word Addressable (GATE 2004)
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AAI JE (IT) 2018 - Q74
How are 2 memory access required here? Only R3 contains a memory address which will be accessed for the operand.
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RISC processor doubt
is the CPI of RISC processor always 1?
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Zeal Test Series 2019: CO & Architecture - Machine Instruction
i am getting D) answer is c)
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CO & architecture
The arithmetic expression $: (a + b) \ast c - d / e \ast \ast f$ is to be evaluated on a two-address machine, where each operands, the number of registers required to eva...
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Ace test series
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made easy test series
What should I assume as the size of HALT instruction ? HALT instruction comes under which type of instruction
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adressing modes
For Given machine instructionsLW R4 #400L1:LW R1, 0,(R4)LW R2 400(R4)ADDI R3, R1, R2SW R3, 0(R4)SUB R4, R4, #4BNZ R4, L1on a 5 stage pipeline processor, 1 clock cycle per...
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adressing modes
Given 2 machine instructions,LW R4 #400LW R1, 0,(R4)IN second instruction what will be loaded in R1,is it the operand at memory location 400?or some random memory locatio...
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