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Recent activity by lalitver10
2
answers
1
#graph #degreeofgraph
Every simple, undirected, connected and acyclic graph with 50 vertices has at least two vertices of degree one.
Every simple, undirected, connected and acyclic graph with 50 vertices has at least two vertices of degree one.
482
views
answered
Apr 14, 2023
IS&Software Engineering
graph-theory
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–
1
answer
2
Website
int main() { int a = 10; cout<<a++; return 0; } (A) 10 (B) 11 (C) 12 (D) Not defined
int main(){int a = 10;cout<<a++;return 0;} (A) 10(B) 11(C) 12(D) Not defined
801
views
commented
Apr 13, 2023
2
answers
3
Database ER model
An ER diagram is having two strong entities E1 and E2. The relationship between the entities ‘R’ is having partial participation from E1 side and total participation from E2 side with 1:1 cardinality. The entities E1 and E2 are having one multivalued attribute each. How many numbers of relations are required to represent the ER model into the relational model?
An ER diagram is having two strong entities E1 and E2. The relationship between the entities ‘R’ is having partial participation from E1 side and total participation ...
1.0k
views
answered
Apr 13, 2023
Databases
databases
er-diagram
relational-model
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–
1
answer
4
GO Classes Test Series 2024 | Discrete Mathematics | Test 4 | Question: 19
Let $\text{S} = \{0, 1, 2, 3, 4, 5, 6, 7, 8, 9\}.$ What is the possible value of integer $\text{K}$ such that any subset of $\text{S}$ of size $\text{K}$ contains two disjoint subsets of size two, $\{x_{1}, x_{2}\}$ and $\{y_{1}, y_{2}\},$ such that $x_{1} + x_{2} = y_{1} + y_{2} = 9?$ $8$ $6$ $7$ $5$
Let $\text{S} = \{0, 1, 2, 3, 4, 5, 6, 7, 8, 9\}.$ What is the possible value of integer $\text{K}$ such that any subset of $\text{S}$ of size $\text{K}$ contains two dis...
367
views
commented
Jan 20, 2023
Combinatory
goclasses2024-dm-4-weekly-quiz
goclasses
combinatory
pigeonhole-principle
multiple-selects
2-marks
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–
2
answers
5
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 6
We want to represent the decimal number $“1000”$ in one’s complement, two’s complement and sign magnitude representations, respectively, which option correctly represent it? $-7,+8,-0$ $-7,-8,0$ $-7,-8,-0$ $+7,+8,-0$
We want to represent the decimal number $“1000”$ in one’s complement, two’s complement and sign magnitude representations, respectively, which option correctly re...
570
views
commented
Jan 13, 2023
CO and Architecture
tbb-coa-2
co-and-architecture
digital-logic
number-system
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–
0
answers
6
NPTEL Assignment
Question : i. CISC architecture a. Symmetric registers ii. RISC architecture b. Multiple memory references iii. Misalignment c. Condition code register iv. Static data d. Single memory reference Options: i-a,ii-c,iii-b,iv-d i-c,ii-a,iii-b,iv-d i-c,ii-a,iii-b,iv-b i-c,ii-a,iii-d,iv-b
Question : i. CISC architecture a. Symmetric registersii. RISC architecture b. Multiple memory referencesiii. Misalignment c. Condition code regis...
238
views
asked
Jan 12, 2023
CO and Architecture
nptel-quiz
co-and-architecture
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–
1
answer
7
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 8
A two-dimensional array int $a [32] [32]$ where each element takes $2$ byte, cache size $2^{12}$ bytes and line size is $2^6$ bytes. The following program segment is stored in the direct mapped cache. ... ][ j] = 0 If initially cache is empty then total number of compulsory cache miss for storing above array is ________
A two-dimensional array int $a [32] [32]$ where each element takes $2$ byte, cache size $2^{12}$ bytes and line size is $2^6$ bytes. The following program segment is st...
389
views
commented
Jan 10, 2023
CO and Architecture
tbb-coa-2
numerical-answers
co-and-architecture
cache-memory
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0
answers
8
Self Doubt
Question: How NullSpace of the matrix A and the uniqueness of the solution of Ax=b are related ??
Question: How NullSpace of the matrix A and the uniqueness of the solution of Ax=b are related ??
312
views
asked
Dec 24, 2022
Linear Algebra
self-doubt
linear-algebra
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3
answers
9
Which of the following algorithm leads convoy effect?
Which of the following algorithm leads convoy effect? FCFS SJF Priority scheduling All of the above
Which of the following algorithm leads convoy effect?FCFS SJF Priority scheduling All of the above
10.5k
views
comment edited
Dec 12, 2022
Operating System
operating-system
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7
answers
10
GATE IT 2006 | Question: 66
A router has two full-duplex Ethernet interfaces each operating at $100$ $\text{Mb/s}$. Ethernet frames are at least $84$ $\text{bytes}$ long (including the Preamble and the Inter-Packet-Gap). The maximum packet processing time at the router for wirespeed forwarding to be possible is (in microseconds) $0.01$ $3.36$ $6.72$ $8$
A router has two full-duplex Ethernet interfaces each operating at $100$ $\text{Mb/s}$. Ethernet frames are at least $84$ $\text{bytes}$ long (including the Preamble and ...
22.4k
views
commented
Nov 30, 2022
Computer Networks
gateit-2006
computer-networks
lan-technologies
ethernet
normal
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–
4
answers
11
GATE CSE 2022 | Question: 25
Consider the resolution of the domain name $\textsf{www.gate.org.in}$ by a $\text{DNS}$ resolver. Assume that no resource records are cached anywhere across the $\text{DNS}$ servers and that iterative query mechanism is used in the resolution. The number of $\text{DNS}$ query-response pairs involved in completely resolving the domain name is ________________.
Consider the resolution of the domain name $\textsf{www.gate.org.in}$ by a $\text{DNS}$ resolver. Assume that no resource records are cached anywhere across the $\text{DN...
11.6k
views
commented
Nov 21, 2022
Computer Networks
gatecse-2022
numerical-answers
computer-networks
1-mark
application-layer-protocols
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–
5
answers
12
GATE CSE 2006 | Question: 74
Consider two cache organizations. First one is $32 \; \textsf{KB}\;2\text{-way}$ set associative with $32 \; \text{byte}$ block size, the second is of same size but direct mapped. The size of an address is $32\; \text{bits}$ in both cases . A $2\text{-to-}1$ multiplexer has ... The value of $h_1$ is: $2.4 \text{ ns} $ $2.3 \text{ ns}$ $1.8 \text{ ns}$ $1.7 \text{ ns}$
Consider two cache organizations. First one is $32 \; \textsf{KB}\;2\text{-way}$ set associative with $32 \; \text{byte}$ block size, the second is of same size but dire...
29.4k
views
commented
Nov 17, 2022
CO and Architecture
gatecse-2006
co-and-architecture
cache-memory
normal
+
–
4
answers
13
GATE CSE 2006 | Question: 75
Consider two cache organizations. First one is $32$ $kB$ $2$-way set associative with $32$ $byte$ block size, the second is of same size but direct mapped. The size of an address is $32$ $bits$ in both cases . A $2$-to-$1$ multiplexer has latency of $0.6 ns$ while a $k-$ ... of direct mapped is $h_2$. The value of $h_2$ is: $2.4$ $ns$ $2.3$ $ns$ $1.8$ $ns$ $1.7$ $ns$
Consider two cache organizations. First one is $32$ $kB$ $2$-way set associative with $32$ $byte$ block size, the second is of same size but direct mapped. The size of an...
11.4k
views
commented
Nov 17, 2022
CO and Architecture
gatecse-2006
co-and-architecture
cache-memory
normal
+
–
6
answers
14
GATE CSE 2014 Set 2 | Question: 55
Consider the main memory system that consists of $8$ memory modules attached to the system bus, which is one word wide. When a write request is made, the bus is occupied for $100$ nanoseconds (ns) by the data, address, and control signals. ... bus at any time. The maximum number of stores (of one word each) that can be initiated in $1$ millisecond is ________
Consider the main memory system that consists of $8$ memory modules attached to the system bus, which is one word wide. When a write request is made, the bus is occupied ...
27.2k
views
commented
Nov 17, 2022
Operating System
gatecse-2014-set2
operating-system
memory-management
numerical-answers
normal
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–
0
answers
15
University Assignment
𝑙𝑜𝑜𝑝: 1. 𝐴𝐷𝐷𝐼 𝑅2, 𝑅2, #1 2. 𝐿𝐷 𝑅4, 0(𝑅3) 3. 𝐿𝐷 𝑅5, 4(𝑅3) 4. 𝐴𝐷𝐷 𝑅6, 𝑅4, 𝑅5 5. 𝑀𝑈𝐿 𝑅4, 𝑅6, 𝑅7 6. 𝑆𝑈𝐵𝐼 𝑅3, 𝑅3, #8 7. 𝐵𝑁𝐸𝑍 𝑅2, 𝑙𝑜𝑜𝑝 8. 𝐴𝐷𝐷 𝑅11, 𝑅12, 𝑅13 Question: Assume a 5-stage pipeline (IF ID EX MEM WB) ... All stages take 1 cycle. Again, the loop takes one iteration to complete. Which dependencies from part (a) cause stalls? How many cycles does the loop take to execute?
𝑙𝑜𝑜𝑝:1. 𝐴𝐷𝐷𝐼 𝑅2, 𝑅2, #12. 𝐿𝐷 𝑅4, 0(𝑅3)3. 𝐿𝐷 𝑅5, 4(𝑅3)4. 𝐴𝐷𝐷 𝑅6, 𝑅4, 𝑅55. 𝑀𝑈𝐿 𝑅4, 𝑅6...
433
views
asked
Nov 14, 2022
CO and Architecture
pipelining
co-and-architecture
loop
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–
1
answer
16
B+ Tree
Which of the following statement true about B tree and B+ tree index? Assume order of B tree node same as order of B+ tree node. A. B tree index has more levels than B+ tree index for large number of keys. B. B+ tree index has more levels than B ... tree best for sequential access of records. D. B+ tree index nodes more than B+ tree for large number of keys. Please Explain every Point.
Which of the following statement true about B tree and B+ tree index? Assume order of B tree node same as order of B+ tree node.A. B tree index has more levels than B+ tr...
1.4k
views
commented
Nov 13, 2022
Databases
databases
b-tree
indexing
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–
0
answers
17
Trishna's GATE CSE
In a programmed I/O technique, the processor is stuck in a wait loop doing status checking of an I/O device. To increase efficiency, the I/O software could be writ- ten so that the processor periodically checks the status of the device. If the device is not ready, ... The printing rate is slowed to 5 CPS (C) The printing rate is at 10 CPS only (D) The printing rate is at 20 CPS
In a programmed I/O technique, the processor is stuckin a wait loop doing status checking of an I/O device.To increase efficiency, the I/O software could be writ-ten so t...
539
views
commented
Nov 3, 2022
Computer Networks
operating-system
input-output
loop
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–
1
answer
18
Routers and bridges
Can we connect LAN and WAN using bridges?? What is the problem, i think there is no problem except expansion of broadcast domain..
Can we connect LAN and WAN using bridges??What is the problem, i think there is no problem except expansion of broadcast domain..
281
views
answered
Oct 31, 2022
Computer Networks
computer-networks
routers-bridge-hubs-switches
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1
answer
19
MadeEasy Subject Test 2019: Computer Networks - Network Switching
877
views
comment edited
Oct 30, 2022
Computer Networks
made-easy-test-series
computer-networks
network-switching
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1
answer
20
this similar question was discussed in GO classes C programming video lectures by (sachin mittal sir.)
i have typed the following code but when i executed it the solution was not according to my expectation.unsigned short int y= -9; int iy=y; printf(“%d”,iy); solutio...
345
views
comment edited
Oct 7, 2022
Programming in C
programming-in-c
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–
1
answer
21
Gate At Zeal
426
views
comment edited
Oct 4, 2022
CO and Architecture
test-series
zeal
co-and-architecture
pipelining
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–
1
answer
22
Doubt.
How pipelining process occurs in SR protocol? will it minimize the Tt time?
How pipelining process occurs in SR protocol? will it minimize the Tt time?
341
views
answered
Sep 29, 2022
Computer Networks
computer-networks
pipelining
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–
2
answers
23
igate test series
The instruction pipeline of RISC processor has 200 instruction in which 100 are performing addition, 25 performing division and 75 are performing multiplication, where Execution state for addition take 1 clock, multiplication take 3 clock cycles and division take 5 clock cycles. Assume pipeline ... wrong. approch totel 200 in which (100 add having 1 cc) +(25*5-1) +(75*(3-1))=354
The instruction pipeline of RISC processor has 200 instruction in which 100 are performing addition, 25 performing division and 75 are performing multiplication, where Ex...
495
views
answered
Sep 29, 2022
CO and Architecture
co-and-architecture
pipelining
numerical-answers
i-gate-test-series
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–
1
answer
24
https://www.indiabix.com/networking/subnetting/004004
Using the following illustration, what would be the IP address of E0 if you were using the eighth subnet? The network ID is 192.168.10.0/28 and you need to use the last available IP address in the range. The zero subnet should not be considered valid for ... 192.168.10.142 B. 192.168.10.66 C. 192.168.100.254 D. 192.168.10.143 E. 192.168.10.126
Using the following illustration, what would be the IP address of E0 if you were using the eighth subnet? The network ID is 192.168.10.0/28 and you need to use the last a...
805
views
comment edited
Sep 21, 2022
Computer Networks
subnetting
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–
2
answers
25
University Assignment
Question → Consider a system in which bus cycles take 500 ns. Transfer of bus control in either direction, from processor to I/O device or vice-versa, takes 250 ns. One of the I/O devices has a data transfer rate of 50 KB/s and employs DMA. ... For how long would the device tie up the bus when transferring a block of 128 bytes? b)Repeat the calculation for cycle-stealing mode
Question → Consider a system in which bus cycles take 500 ns. Transfer of bus control in either direction, from processor to I/O device or vice-versa, takes 250 ns. One...
759
views
answered
Sep 19, 2022
CO and Architecture
computer-peripherals
dma
moderate
+
–
1
answer
26
% time of CPU blocked in DMA
Please Explain the formulae for % time of CPU blocked in both Cycle Stealing mode and Burst mode of DMA
Please Explain the formulae for % time of CPU blocked in both Cycle Stealing mode and Burst mode of DMA
8.3k
views
comment edited
Sep 18, 2022
CO and Architecture
co-and-architecture
dma
+
–
1
answer
27
Gate At Zeal
Question → If (G,*) is a group of order 960 and there exist a in G such that a^m=e for some integer m<=960 where e is identity element of G then total number of possible value of m is___________ Answer==28
Question → If (G,*) is a group of order 960 and there exist a in G such that a^m=e for some integer m<=960 where e is identity element of G then total number of possibl...
498
views
asked
Sep 17, 2022
Set Theory & Algebra
group-theory
discrete-mathematics
test-series
zeal
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–
1
answer
28
Test Series
Question : Consider a Device which operates with 20 MBPS operating speed.The device is operating on Programmed control mode of I/O and it has to transfer data of 20 B from it the data is transferred byte wise .Size of status register is 2 Bytes.total time needed to perform the data transfer is --------(microseconds)
Question : Consider a Device which operates with 20 MBPS operating speed.The device is operating on Programmed control mode of I/O and it has to transfer data of 20 B fro...
695
views
asked
Sep 16, 2022
CO and Architecture
co-and-architecture
input-output
test-series
+
–
5
answers
29
GATE CSE 2005 | Question: 69
A device with data transfer rate $10$ KB/sec is connected to a CPU. Data is transferred byte-wise. Let the interrupt overhead be $4\mu$sec. The byte transfer time between the device interface register and CPU or memory is negligible. What is ... gain of operating the device under interrupt mode over operating it under program-controlled mode? $15$ $25$ $35$ $45$
A device with data transfer rate $10$ KB/sec is connected to a CPU. Data is transferred byte-wise. Let the interrupt overhead be $4\mu$sec. The byte transfer time between...
19.7k
views
comment edited
Sep 16, 2022
CO and Architecture
gatecse-2005
co-and-architecture
interrupts
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–
1
answer
30
In Go-back-N protocol with m=6, the sending machine is in the ready state with Sf=10 and Sn=15, An ACK with ACKNo =13 arrives, what are the next values of Sf, Sn and Rn?
1.4k
views
answered
Sep 16, 2022
Computer Networks
go-back-n
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