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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2024-1} & \textbf{2024-2} & \textbf{2023} &  \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 2&2&2& 3 &1&2&1&2&3
\\\hline\textbf{2 Marks Count} & 3&3&4& 2 &2&2&2&2.67&4
\\\hline\textbf{Total Marks} & 8&8&10& 7 &5&6&\bf{5}&\bf{7.33}&\bf{10}\\\hline
\end{array}}}$$

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#2721
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speedup
Assume we have a computer where the cycles per instruction (CPI) is 1.0 when all memory accesses hit in the cache.The only data accesses are loads and stores, and these total ... be if all instructions were cache hits? 1.5 0.7 2.75 1.75
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#2722
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GATE CSE 1987 | Question: 1-ix
The refreshing rate of dynamic RAMs is in the range of$2$ microseconds$2$ milliseconds.$50$ milliseconds$500$ milliseconds
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#2723
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2 answers
12 votes
GATE CSE 1987 | Question: 1-viii
On receiving an interrupt from a I/O device the CPU:Halts for a predetermined time.Hands over control of address bus and data bus to the ... .Branches off to the interrupt service routine after completion of the current instruction.
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#2724
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2 answers
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GATE CSE 1987 | Question: 1-vi
A microprogrammed control unitIs faster than a hard-wired control unit.Facilitates easy implementation of new instruction.Is useful when very small programs are to be run.Usually refers to the control unit of a microprocessor.
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#2725
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6 answers
45 votes
GATE CSE 1987 | Question: 1-V
The most relevant addressing mode to write position-independent codes is:Direct modeIndirect modeRelative modeIndexed mode
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#2726
736
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0 answers
3 votes
Carl Hamatcher Pg 469, Instruction Hazards
In this Example of Branch folding I'm not getting how instruction I3 and I5 can Decode in same cycle i.e. cycle 6. and How instruction queue is helping Here to make Execution of Instruction faster
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#2727
807
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addresses
can someone explain the difference in logical address,physical address and virtual address explained in Oerating system and co& architecture??logical address is ... address??what is meant by virtual to physical address translation??
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#2728
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1 answers
6 votes
Relative Addressing Mode
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#2729
444
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1 answers
3 votes
flip flop
1. The output of a flip flop changes once the input changes2. Flip flop is a typical synchronous astable device devicewhich of the following is truea) only 1 b)only 2 c)both 1 and 2 d) neither
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#2730
258
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1 answers
1 votes
DMA is
DMA is a)Processor by itself b) Feature of the computer c)Part of processor d)A dedicated h/w device
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#2731
842
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valid class of interrupts
which of the following is valid class of interrupts 1)program 2)timer 3)I/O 4) h/w failurea)1 and 3b)2 and 3 c)1,2 and 4 4)None
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#2732
375
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1 answers
1 votes
ME-Practice Book COA Q#
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#2733
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1 answers
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ME-Practice Book COA Q#48
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#2734
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ME-Practice Book COA Q#34
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#2735
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ME-Practice Book COA Q#14-15
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#2736
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ME-Practice Book COA Q#10
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#2737
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1 answers
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ME-Practice Book COA Q#8-9
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#2738
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ME-PracticeSet-COA Q#53
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#2739
322
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1 answers
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ME-PracticeSet-COA Q#54
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#2740
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ME-PracticeSet-COA Q#44
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