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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2024-1} & \textbf{2024-2} & \textbf{2023} &  \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 2&2&2& 3 &1&2&1&2&3
\\\hline\textbf{2 Marks Count} & 3&3&4& 2 &2&2&2&2.67&4
\\\hline\textbf{Total Marks} & 8&8&10& 7 &5&6&\bf{5}&\bf{7.33}&\bf{10}\\\hline
\end{array}}}$$

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Recent questions in CO and Architecture

#2621
411
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1 answers
1 votes
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 1
We have two implementations of the same Instruction Set Architecture (ISA). Machine $A$ has a clock cycle time of $50$ ns and a CPI of $4.0$ for a program, ... than B.Machine B is faster than A.Both have the same speed.None of the above
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#2622
444
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0 answers
1 votes
Self Made
In pipelining, what is the need of interstate buffer?We are anyway setting the clock equal to the longest delay. The output of one stage will not come out untill the end of one clock cycle.So why do we need the buffer?
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#2623
2.5k
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1 answers
2 votes
No of clock cycles
Consider the following sequence of instructions executed on the five-stage pipelined processor:Assuming there is no forwarding, calculate the number of clock cycles needed to execute above program ?
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#2624
4.8k
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2 answers
4 votes
pipeline speedup
You are given a non-pipelined processor design which has a cycle time of 10ns and average CPI of 1.4.If a pipelined processor having 5 stages are 1ns, 1.5ns, 4ns, ... ,CPI=1.4 is not considered for CTold...That i am not able to understand.
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#2625
2.2k
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1 answers
10 votes
GATE CSE 1990 | Question: 8a
A single bus CPU consists of four general purpose register, namely, ... suitable microinstructions, write a microroutine for the instruction, $\text{ADD }R0, R1$.
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#2626
680
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1 answers
1 votes
Made Easy Test Series cache Memory
consider a 32 bit microprocessor which has 32K byte which is 4-way set associative cache.Block size of cache is 2 32-bit words.The set number to which wprd from memory ... as block size .Answer given was based on <Tag,Set,Word> =<19,9,4>
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#2627
611
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1 answers
3 votes
seedup due to pipelining
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#2628
470
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1 answers
0 votes
#Pipelining
Consider a non-pipelined processor design with clock cycle time zones and average CPI 1.5. Now it is decided to shift pipeline processor, it has 5 stages taking ... time for 2 cycles. Then what is the new CPI of the pipelined processor?
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#2629
457
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0 answers
0 votes
Cache Coherence problem and how it can be solved?
Cache Coherence problem and how it can be solved please explain
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#2630
477
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1 answers
0 votes
MadeEasy Test Series: CO & Architecture - Cache Memory
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#2631
800
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2 answers
1 votes
MadeEasy Test Series: CO & Architecture - Cache Memory
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#2632
30.0k
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1 answers
40 votes
GATE CSE 1990 | Question: 7a
A block-set associative cache memory consists of $128$ blocks divided into four block sets. The main memory consists of $16, 384$ blocks and each block contains ... memory?How many bits are needed to represent the TAG, SET and WORD fields?
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#2633
2.8k
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0 answers
4 votes
GATE CSE 1990 | Question: 4-iv
State whether the following statements are TRUE or FALSE with reason:Transferring data in blocks from the main memory to the cache memory enables an interleaved main memory unit to operate at its maximum speed.
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#2634
3.4k
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3 answers
9 votes
GATE CSE 1990 | Question: 4-iii
State whether the following statements are TRUE or FALSE with reason:The flags are affected when conditional CALL or JUMP instructions are executed.
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#2635
7.8k
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4 answers
19 votes
GATE CSE 1990 | Question: 4-ii
State whether the following statements are TRUE or FALSE with reason:The data transfer between memory and I/O devices using programmed I/O is faster than interrupt-driven I/O.
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#2636
3.8k
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2 answers
2 votes
What is WAW , WAR and RAW in data hazards please tell
What is WAW , WAR and RAW in data hazard
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#2637
11.0k
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2 answers
18 votes
pipeline_hazard
no of RAW,WAR and WAW ?
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#2638
414
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0 answers
1 votes
self doubt related to program counter
As PC points to the next instruction to be executed.When the last instruction will execute , What will be the value of program counter?
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#2639
1.8k
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1 answers
5 votes
MadeEasy Test Series: CO & Architecture - Addressing Modes
Here we will consider memory as word addressable or byte addressable?
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#2640
616
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2 answers
1 votes
Word addressable memory
If the memory size would be 512KB then should we devide by 32?
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