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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2024-1} & \textbf{2024-2} & \textbf{2023} &  \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 2&2&2& 3 &1&2&1&2&3
\\\hline\textbf{2 Marks Count} & 3&3&4& 2 &2&2&2&2.67&4
\\\hline\textbf{Total Marks} & 8&8&10& 7 &5&6&\bf{5}&\bf{7.33}&\bf{10}\\\hline
\end{array}}}$$

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#2561
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GATE CSE 1989 | Question: 7
An 8085-based microcomputer consisting of 16 kbytes of ROM, 16kbytes of RAM and four 8-bit I/O ports is to be designed using RAM and ROM chips each of 2 ... to occupy lower order I/O address space.Give memory map and I/O address map.
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#2562
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GATE CSE 1989 | Question: 6b
In a certain computer system, there is special instruction implemented to call subroutines. The instruction isJSR Reg.Sub Microsequence: Temp ← Sub SP ← (SP)+ ... control flow diagram and the contents of the stack before and after the call.
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#2563
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GATE CSE 1989 | Question: 6a
A certain computer system was designed with cache memory of size $1$ Kbytes and main memory size of $256$ Kbytes. The cache implementation was fully ... a change in the program size of model to improve the hit ratio significantly.
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#2564
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2 answers
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MadeEasy Test Series: Programming & DS - Programming In C
answer?
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#2565
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1 answers
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MadeEasy Test Series: CO & Architecture - Pipelining
nothing is given regarding when the effective address of target instruction is available is given, what to assume?
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#2566
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cycle stealing
The storage area of a disk has the innermost diameter of 10 cm. and outermost of 20 cm., maximum recording density is 1400 bits/cm., the disk rotates at ... for data transfer, what is the % of memory cycles stolen for transferring 1 word.
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#2567
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DMA-VG
Consider a hard disk which when requested to read a sector of 2048 bytes, first reads into its own local memory, and then uses DMA to transfer it ... it take to complete the transfer? All possible pipelining between stages is implemented.
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#2568
529
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2 answers
1 votes
ace test CO-I
A two-way set associative cache memory uses blocks of four words. The cache can accomodate a total of 2048 words from main memory. the main memory size is 128Kx32. What ... size of the cache memory ?A) 1024*32B) 1024*78C) 1024*64D) 1024*96
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#2569
483
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1 answers
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ace test CO-I
If a level of memory hierachy has a hit rate of 75%, memory request takes 12 ns to complete if they hit in the level,and the memory request that miss in the level take 100 ns to complete. The average access time of the level is_________ns
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#2570
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ME COA
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#2571
241
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3 votes
ME FLT-2
i got 0.092ns but how it is 92MIPS?
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#2572
160
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–2 votes
Q 40 made easy.gate 2016
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#2573
202
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–1 votes
2006 byte addressable memory question
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#2575
312
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1 answers
1 votes
MadeEasy Test Series: CO & Architecture - Cache Memory
here i think here words are also considered but in the solution its not taken plz check..i also know its herarichal system.
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#2576
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MadeEasy Test Series: CO & Architecture - Addressing Modes
Q. Consider an instruction of indirect addressing mode. what is the number of memory refrence by the processor when instruction is a computation that require a single operand and when it is a ... 3,3 C)3,2 D) 2,3
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#2577
597
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2 answers
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MadeEasy Test Series: CO & Architecture - I/O Handling
#plz check??
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#2578
216
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Self Made
Are questions regarding number of RAM chips, ROM chips there in syllabus, or have they been removed from the new syllabus??
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#2579
793
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1 answers
4 votes
dma,harddisk
Consider a hard disk which when requested to read a sector of 2048 bytes, first reads into its own local memory, and then uses DMA to transfer it to the main memory over ... . (A) 10250ns (B) 10330ns (C) 10360ns (D) None of these
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#2580
609
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1 answers
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structural hazards
Can we completely remove structural hazards..if we have separate intruction memory and data memory?
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