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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2024-1} & \textbf{2024-2} & \textbf{2023} &  \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 2&2&2& 3 &1&2&1&2&3
\\\hline\textbf{2 Marks Count} & 3&3&4& 2 &2&2&2&2.67&4
\\\hline\textbf{Total Marks} & 8&8&10& 7 &5&6&\bf{5}&\bf{7.33}&\bf{10}\\\hline
\end{array}}}$$

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#2521
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How to add two numbers BC and AF in microprocessor language?
How to add two numbers BC and AF in microprocessor language?
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#2522
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1 answers
5 votes
find the page table size
Consider the following memory organization of a processor. The virtual address is 40 bits, the physical address is 32 bits, the page size is 8 KB. The processor has a 4 ... 64 bytes.What is the total size of the page table? 8MB 10MB 2MB
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#2523
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Ace test series
A DRAM chip is designed with capacity of 512MBytes with row size of 32 bits each, one refresh operation takes one nanosecond time.Total refresh time to ... . My answer is 134.22 milliseconds while the answer given is 128 milliseconds.
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#2524
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#co-cache
i'm getting 37.2 =37 but given 32 ...
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#2525
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1 answers
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Number of stall cycles for given speed up
Anyone? I know my answer is wrong.
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#2526
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Direct mapping
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#2527
245
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CACHE MAPPING
What is the no.of multiplexer user in Set Associative Cache Mapping ? After CPU generates the Address ,1st Set bits are checked(Are these set bits ,extra space ... to comaparator where it is matched to the tag of address generated by CPU.
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#2528
729
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1 answers
2 votes
general conceptual doubt
Why increase in cache size doesnt affect conflict misses??According to me when we will increase cache size number of blocks will increase and hence lesser no of ... miss is independent of cache size how?? This seems so confusing to me.
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#2529
921
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2 answers
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Memory refrences
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#2530
828
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1 answers
1 votes
Coa+ Stalls+ Speed up
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#2531
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1 answers
1 votes
MadeEasy Workbook [2017] Q33 - Efficiency of Cache using Write Through Scheme
Data:Hit Ratio for Read Op - 80%Hit Ratio for Write Op - 90%There are 30% updations.Cache Access time: 20ns [CMAT]MM Access Time - 100ns [MMAT]If there is a miss ... Ops per secPlease tell me if it's right or wrong or how it will be solved.
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#2532
286
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1 answers
0 votes
Pick primary memory
.
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#2533
4.2k
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3 answers
28 votes
GATE CSE 1988 | Question: 2-ii
Using an expanding opcode encoding for instructions, is it possible to encode all of the following in an instruction format shown in the below figure. Justify your answer. ...
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#2534
11.2k
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2 answers
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Expanding opcode technique
A CPU is designed to have 58 three-address instructions and 25 two-address instructions. The CPU is able to address a maximum of 16 memory ... length of the machine codev) List the machine codesDetailed explanation would be helpful
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#2535
198
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2 votes
Stalls in CO
Delayed branching is used to avoid stalls, But Is it used to solve dependencies?Ques:: Which of the following harzards can be minimized by instruction reordering?a. Structural dependencyb.Control dependencyc. Data Hazardsc. None
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#2536
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explain
WAR hazard can happen in pipelines that support auto-increment operation.What does this mean?
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#2537
171
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Help if you know
I read somewhere that WAW hazard is present only in pipelines that write in more than one pipe stage or allow an instruction to proceed even when previous instruction is stalled.Please explain me what is meant by this line by line.
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#2538
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Cache+memory
I am not understanding how options are given because even when one miss will occur entire cache block will be accessed, so 128 B will be accessed.
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#2539
4.0k
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4 answers
21 votes
MadeEasy Test Series: CO & Architecture - Cache Memory
Suppose that in 250 memory references there are 30 misses in first level cache and 10 misses in second level cache. Assume that miss penalty from L$_2$ cache ... = 1800-1250 = 550number of stalls/instruction= 550/200 = 2.75please verify
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#2540
772
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1 answers
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Register data transfer
Registers R1 and R2 contain memory address and data to be written in that memory adress respectively. To execute the instruction that transfers content of R2 to ... R1MDR <- R2Can both of these operations be performed in same clock cycle?
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