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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2024-1} & \textbf{2024-2} & \textbf{2023} &  \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 2&2&2& 3 &1&2&1&2&3
\\\hline\textbf{2 Marks Count} & 3&3&4& 2 &2&2&2&2.67&4
\\\hline\textbf{Total Marks} & 8&8&10& 7 &5&6&\bf{5}&\bf{7.33}&\bf{10}\\\hline
\end{array}}}$$

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Recent questions in CO and Architecture

#2501
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2 answers
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Carl Hamcher
Assume that 20 percent of the dynamic count of the instructions executed for a program are branch instructions. Assume further that 75 percent of branches ... actually 90 percent, what is the speedup relative to using static prediction?
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#2502
139
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0 answers
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# CO Dout
1 word is equal to how many bytes or is there is way to calculate from given scenario??
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#2503
424
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1 answers
0 votes
explain
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#2504
335
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polling
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#2505
256
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MadeEasy Subject Test: CO & Architecture - Dma
Consider a disk drive with 16 surfaces, 512 tracks / surface, 256 sectors / track, 8 KB / sector with a rotation speed of 3600 rpm. The disk is ... maximum percentage of time that the CPU gets blocked during DMA operation is __________ .
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#2506
3.8k
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1 answers
13 votes
GATE CSE 1988 | Question: 9iii
In the program scheme given below indicate the instructions containing any operand needing relocation for position independent behaviour. Justify your answer. ...
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#2507
536
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0 answers
1 votes
GATE CSE 1988 | Question: 9ii
The code for the implementation of a sub-routine to convert positive numeric data from binary to appropriate character string in a $PDP-11$ like machine has been given belowNote- ...
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#2508
1.8k
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3 answers
7 votes
GATE CSE 1988 | Question: 9i
The following program fragment was written in an assembly language for a single address computer with one accumulator register:LOAD B MULT C STORE T1 ADD ... MULT T2 ADD T1 STORE ZGive the arithmetic expression implemented by the fragment.
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#2509
282
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0 answers
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GATE CSE 1988 | Question: 5ii
Briefly explain the term “Configuring a programmable peripheral chip”.
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#2510
544
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0 answers
1 votes
GATE CSE 1988 | Question: 5i
A ROM has the following time parameters:Maximum Address to valid Data Output delay $= 30$ n sec.Maximum Chip Select to valid Data Output delay $= 20$ n ... a CPU can continuously read data from this ROM?(Show your calculations step-by-step)
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#2511
559
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0 answers
1 votes
GATE CSE 1988 | Question: 4i
An $8$-bit data path is to be set up using two $4$-bit ALU's and suitable multiplexers. The ALU's accept two operands $A$ and $B$ on ... and estimate the minimum width of a signal microcode word needed for the generation of these signals.
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#2512
588
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2 answers
1 votes
interrupt
Whenever a interrupt generates..mode changes(user to kernel mode)?
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#2513
198
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0 answers
0 votes
self doubt
I am confused between memory mapped IO and Isolated IOI read that for large amount of data transfer memory mapped io are used because they have variety of ... fast.Now from these two statements how to infer which one is fast/better?
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#2514
436
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0 answers
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William Stalling cache memory || 4.22
A computer has a cache, main memory, and a disk used for virtual memory. If a referenced word is in the cache, 20 ns are required to access it. ... is the average time in nanoseconds required to access a referenced word on this system?
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#2515
665
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1 answers
5 votes
Cache memory
Cache memory with a line size of $\large\color{maroon}{\text{32}}$B. In a cache miss situation block of words are loaded from Main memory ... before being replaced such that write back policy becomes more effective than write-through?
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#2516
1.4k
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1 answers
3 votes
William Stalling cache memory || 4.21
Consider a $\color{maroon}{\text{single-level cache}}$ with an access time of $2.5$ ns, a line size of $64$ ... $0.97$. Does this reduce the average memory access time?
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#2517
605
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1 answers
0 votes
SELF DOUBT
Consider a hard disk with 16 recording surfaces (0-15) having 16384 cylinders (0-16383) and each track contains 64 sectors (0-63). Data storage capacity in ... I SHOULD CONVERT 5200 INTO CHS OR 5199 BECAUSE SECTOR NO STARTS WITH 0??
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#2518
157
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0 answers
0 votes
pipeline
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#2519
351
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1 answers
0 votes
ROM chip -----Plz explain......
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#2520
365
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0 answers
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Hazards
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