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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2024-1} & \textbf{2024-2} & \textbf{2023} &  \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 2&2&2& 3 &1&2&1&2&3
\\\hline\textbf{2 Marks Count} & 3&3&4& 2 &2&2&2&2.67&4
\\\hline\textbf{Total Marks} & 8&8&10& 7 &5&6&\bf{5}&\bf{7.33}&\bf{10}\\\hline
\end{array}}}$$

Recent questions in CO and Architecture

#2581
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1 answers
0 votes
how to calculate tag directory size in direct cache mapping...is it number of lines * tag bits??
#2582
6.2k
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3 answers
30 votes
#2583
1.2k
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1 answers
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Consider the following instructions of an 8085 microprocessorMVI D, 6 EHMVI E, 5 DHMOV A, DADD EIf above sequence of instructions are executed, then the value of carry flag (CY) and auxiliary ... 0CY = 0, AC = 1CY = 1, AC = 1CY = 1, AC = 0
#2584
767
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1 answers
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Consider the following set of instructions executed by 8085 microprocessorMOV H,20MOV L,10MOV E,00XCHGAfter the execution, the contents of E register will be ______________ (integer value only).
#2585
1.9k
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1 answers
1 votes
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#2586
5.2k
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0 answers
4 votes
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#2587
403
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1 answers
2 votes
#2588
612
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1 answers
3 votes
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#2589
933
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1 answers
3 votes
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#2590
17.2k
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2 answers
4 votes
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#2591
8.8k
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2 answers
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#2592
742
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1 answers
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#2593
462
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1 answers
1 votes
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#2594
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#2595
266
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1 answers
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#2596
424
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1 answers
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#2597
301
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1 answers
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#2598
514
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#2599
485
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