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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2024-1} & \textbf{2024-2} & \textbf{2023} &  \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 2&2&2& 3 &1&2&1&2&3
\\\hline\textbf{2 Marks Count} & 3&3&4& 2 &2&2&2&2.67&4
\\\hline\textbf{Total Marks} & 8&8&10& 7 &5&6&\bf{5}&\bf{7.33}&\bf{10}\\\hline
\end{array}}}$$

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#2601
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Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 24
Consider two pipelines A and B. Pipeline A has $8$ stages with uniform stage delay of $2$ns. Pipeline B has $5$ stages with uniform stage delays of $3$ ... in ns) by pipeline A compared to pipeline B to execute $100$ instructions is _____.
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#2602
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Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 19
In an $8$ segment pipeline, the total number of clock pulses that process $150$ tasks are ______ cycles.
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#2603
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3 answers
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Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 20
A computer has $32$ bit instructions and $12$ bit addresses.If there are $250$ two-address instructions, the number of one-address instructions that can be formulated are ______.
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#2604
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Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 21
In a computer system, there are $5$ registers, namely -- $PC, AR, DR, IR,$ and $SC$. The initial content of $PC$ is $7FF$. The content of ... $PC$ register after $6$ clock pulse is ________ (put the integer value of register content).
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#2605
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Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 16
A pipelined processor has two branch delay slots. An optimizing compiler can fill one of these slots $85$ % of the time, and can fill ... , then the percentage improvement in performance achieved by this optimization is ________%.
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#2606
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Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 17
The fastest mode of data transfer is:Programmable I/OInterrupt I/ODMABoth A and B
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#2607
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Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 18
In a system, cache memory access time is $100ns$ and the main memory is $10$ times slower than cache memory. The hit ratio for read request is $0.92$ ... (in ns) considering both read & write requests (using write-through policy) is ______.
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#2608
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Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 13
A non-pipeline system takes $25$ ns to process a task. The same task can be processed in a six-segment pipeline in a clock cycle of $10$ ns.The speed-up rotation of the pipeline for $10$ tasks will be _______.
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#2609
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Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 14
A disk has $20$ sectors per track. Assume there are $512$ bytes per sector. What is the data transfer rate (in bytes per second) at a rotational speed of $7200$ rpm? ... $1.318 * 10^5$ bytes/second$1.2288 * 10^6$ bytes/second
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#2610
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Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 15
An instruction is stored at location $300$ with its address field at location $301$. The address field has a value of $400$ ... the instruction (with $R1$ as index register) then the effective address is _________.
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#2611
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Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 10
Registers $R1$ and $R2$ of a computer contain the decimal values $1300$ and $4500$. The following instructions are run:$\text{ Load 20(R1),R5}$\text{ ... The effective address of the memory operand is ___________.
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#2612
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Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 11
A system has $3$ levels of cache i.e., $L_1, L_2$ and $L_3.$ The access times of $L_1,L_2$ and $L_3$ cache memories are $100$ ns/word, $150$ ns/word ... gets transferred, what is the average access time? $103$ ns$220$ ns$150$ ns $135$ ns
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#2613
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Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 12
A computer uses a small direct-mapped cache between the main memory and the processor. The cache has four $16$-bit words (the data field), and each word has an ... $4$6$8$
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#2614
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Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 8
A link between the CPU and the user is provided by:Peripheral DevicesStorageControl UnitSoftware
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#2615
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Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 9
A byte-addressable computer has a small data cache capable of holding eight $32$-bit words. Each cache block consists of one $32$-bit word. When a given program is ... . If a direct-mapped cache is used, then the hit rate is __________ $\%$
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#2616
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Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 4
A direct-mapped cache has $2^{10}$ cache lines with $2^4$ bytes of data per cache line. If the cache is used to store blocks for a byte addressable memory of size $2^{30}$ ... the tags? $2^{15}$ bytes $2^{11}$ bytes $2^6$ KB $2^7$ KB
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#2617
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Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 5
Which of the following is displacement addressing mode?RelativeIndexedBaseImmediate
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#2618
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1 answers
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Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 6
An interrupt that can temporarily be ignored by the computer is called: Vectored Interrupt Non-Maskable Interrupt Scalar Interrupt Maskable Interrupt
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#2619
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Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 7
A disk unit has $24$ recording surfaces and a total of $14,000$ cylinders. There is an average of $400$ sectors per track. Each sector contains $512$ bytes of data.What are the maximum ... $68.80 * 10^9$ B $69.87 * 10^9$ B
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#2620
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Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 2
In a seven-segment pipeline, each segment takes $1$ cycle. Assuming there are no stalls, the number of clock cycles required to process $180$ tasks in a seven – segment pipeline is _______ cycles.
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