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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2024-1} & \textbf{2024-2} & \textbf{2023} &  \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 2&2&2& 3 &1&2&1&2&3
\\\hline\textbf{2 Marks Count} & 3&3&4& 2 &2&2&2&2.67&4
\\\hline\textbf{Total Marks} & 8&8&10& 7 &5&6&\bf{5}&\bf{7.33}&\bf{10}\\\hline
\end{array}}}$$

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Recent questions in CO and Architecture

#2681
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2 answers
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Pipelining and CPI
Consider a non-pipelined processor design which has a cycle time of 10ns and average CPI of 1.4. If each pipeline stage adds extra 20ps due to register setup ... the time for 2 cycles (these occurrences are disjoint). What is the new CPI?
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#2682
479
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1 answers
1 votes
cache
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#2683
5.0k
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2 answers
3 votes
No. of Tag bits in Set Associative cache memory.
Consider the memory system in which the block size in cache and main memory are equal. Cache consists of 512 blocks and main memory consists of 8192 blocks. Cache is 4-way set associative ,calculate the number of tag bits in cache?
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#2684
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2 answers
1 votes
cache memory mapping
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#2685
650
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1 answers
0 votes
Cache and arrays
Consider below code written in C Loop Asum = 0; for (i = 0; i < 128; i++) for (j = 0; j < 64; j++) sum += A[i][j]; ... address comprise the tag, index and offset?i)(19,8,8)ii)(20,8,7)iii)(17,8,7)iv)(18,8,6)
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#2686
642
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1 answers
0 votes
Arrays and cache
Consider below code written in C Loop Asum = 0; for (i = 0; i < 128; i++) for (j = 0; j < 64; j++) ... number of cache misses that will occur when running Loop A.i)1392 missesii) 1024 missesiii)1020 missesiv)1323 misses
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#2687
1.5k
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1 answers
3 votes
COA-Floating Point Arithmatic
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#2688
543
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1 answers
0 votes
Write through Updation
Here , in sol. they have obtained ans as :0.35*(max(40,50)) + 0.65 *(40+50) = 76Shouldn't the access times be not considered at all?
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#2689
467
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1 answers
2 votes
#CO-Addressing Modes
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#2690
1.1k
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1 answers
1 votes
Write through Cache
i'm not getting ans
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#2691
274
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0 answers
3 votes
ME-FST1-Q14
Consider the following statements:S1 : Relative mode is the addressing mode which can be used to write code in which reallocation is done at run time.S2 : Indirect ... S1c. Both S1 and S2 are correctd. Neither of S1 or S2 are correct
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#2692
157
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0 answers
1 votes
word read from memory
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#2693
1.8k
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1 answers
3 votes
Disk capacity
Assume innermost track has diameter 1 cm and outermost track has diameter 10 cm. There are 10 tracks in the disk and it is rotating with constant linear velocity. Capacity of innermost track is 1MB. Total capacity of the disk is ____ ?
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#2694
335
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1 answers
1 votes
CO-Pipeline-CPI
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#2695
186
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0 answers
1 votes
Cache
The designer of the processor claims that it will have an average memory latency of 1.5 cycles. The design includes a 1 cycle access to the L1 cache, an ... cache never misses, what has she assumed about the L1 cache hit ratio?Plz explain
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#2696
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1 answers
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Implement a 1K x 16 memory organization using 128 x 8 RAM chips.
Please show working in answer
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#2697
384
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Write down the sequence of control signals required to execute LDA 1000
Write down the sequence of control signals required to execute LDA 1000 instruction (loading the content of 1000 into accumulator) in single bus CPU organisation.Please show working in answer
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#2698
619
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1 answers
1 votes
MadeEasy Test Series: CO & Architecture - Pipelining
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#2699
525
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3 answers
2 votes
MadeEasy Test Series: CO & Architecture - Pipelining
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#2700
431
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0 answers
1 votes
GATE CSE 1987 | Question: 5a
Eight $7$-segment LED displays and a keyboard consisting of $28$ keys are to be interfaced to a microprocessor based system. Give the block diagram of the ... lines from any programmable I/O chip. Use any other IC chip if necessary.
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