Recent questions tagged made-easy-test-series

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a. i>0,K>0, a[K] a[max]b. i>0,K<0, a[K]< a[max]c. i<0,K>0, a[K] a[max]d. i>0,K>0, a[K]< a[max]
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Consider $1 \text{ MBPS}$ hard disk is interfaced to the processor in a cycle stealing mode of $\text{DMA}$ whenever $64$ bytes of the data is available in the buffer the...
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Please explain how they merged.(Modified)
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S: R1(A), R3(D), W1(B), R2(B), R4(B), W2(C), R5(C), W4(E), R5(E), W5(B)Number of serial schedules which are view equal to above S are __.Polygraph that I drew:
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Please explain Statement S3?
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Which of the following statement false is relation R is in 3NF but not BCNF?Relation R must consist atleast two over-lapped candidate keys.Relation R must consist proper ...
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Consider the following FD set {A → BC,B → AC, C → AB}. The number of different minimal covers possible for the above FD set __________ .
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The current trend toward specialization in nearly all occupational groups is exactly the opposite of what the educational system needs. World problems now a days are so d...
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and Solution Given is : Pls explain...
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Shouldn't the number of dependencies be 5 (2 because of R1 & 3 because of R2).
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How option B would confirm - Bounded waiting.??
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A device with data transfer rate of 8 KBps is connected to a CPU. Data is transferred bytewise. Let interrupt overhead be 2 μsec. The byte transfer time between the devic...
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Three 4 bit shift registers are connected in cascade as shown in figure below. Each register is applied withA 4 bit data 1011 is applied to the shift register 1. What is ...
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I have gone through these types of questions but I'm unable to understand. how to appraoch these questions? And during the dma transfer, cpu is considered to be idle. bef...
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How are the delay registers to be considered?