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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2024-1} & \textbf{2024-2} & \textbf{2023} &  \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 2&2&2& 3 &1&2&1&2&3
\\\hline\textbf{2 Marks Count} & 3&3&4& 2 &2&2&2&2.67&4
\\\hline\textbf{Total Marks} & 8&8&10& 7 &5&6&\bf{5}&\bf{7.33}&\bf{10}\\\hline
\end{array}}}$$

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Recent questions in CO and Architecture

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2861
#Set Associative Memory #computer architecture
Q. A set-associative cache consist of 60 lines,or blocks,divided into four-line sets. Main memory consist of 2K blocks of 512 works each. In the format of main memory addresses, what is the size of tag , set and word is?
Q. A set-associative cache consist of 60 lines,or blocks,divided into four-line sets. Main memory consist of 2K blocks of 512 works each. In the format of main memory add...
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1 answer
2862
pipelining
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2863
pipelining
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2864
pipelining
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2 votes
1 answer
2866
UGC NET CSE | December 2010 | Part 2 | Question: 34
The register or main memory location which contains the effective address of the operand is known as Pointer Special location Indexed register None of the above
The register or main memory location which contains the effective address of the operand is known asPointerSpecial locationIndexed registerNone of the above
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2869
Memory-Control Unit
If size of MAR &MBR are $32$ bit and $16$ bit respectively then what is the main memory size. if memory is byte addressable .
If size of MAR &MBR are $32$ bit and $16$ bit respectively then what is the main memory size.if memory is byte addressable .
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2875
William Stalling External Memory Exercise-01
william stalli n g
william stalli n g
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2 votes
1 answer
2876
harddisk
A disk pack has 19 surfaces and storage area on each surface has an outer diameter of 33cm and inner diameter of 22cm .The maximum recording storage density on any track is 200 bits/cm and minimum spacing between tracks is 0.25 mm, then calculate the capacity of disk pack?
A disk pack has 19 surfaces and storage area on each surface has an outer diameter of 33cm and inner diameter of 22cm .The maximum recording storage density on any track ...
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0 votes
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2878
Hard disk
A hard disk system has the following parameters: Number of tracks = 512, Number of sectors/track = 256, Number of bytes /sector = 64, Seek time = 256 ms, Rotation speed = 600 rpm. What is the average time taken for transferring 4 KB from the disk is_________ ms.
A hard disk system has the following parameters: Number of tracks = 512, Number of sectors/track = 256,Number of bytes /sector = 64, Seek time = 256 ms, Rotation speed = ...
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1 votes
1 answer
2879
Hard disk
If a disk system has an average seek time of 30 ns and rotational rate of 360 rpm. Each track of the disk has 512 sectors each of size 512 bytes. a) What is the time required to read 4 successive sectors? b) What is the data transfer rate?
If a disk system has an average seek time of 30 ns and rotational rate of 360 rpm. Each track of the disk has 512 sectors each of size 512 bytes.a) What is the time requ...
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3 votes
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2880
DMA CONTROLLER CYCLE STEALING
Please explain DMA cycle stealing mode with a timeline diagram. Does the DMA wait for 1 byte before aquiring the bus control and is this the same time when CPU utilizes the bus for it's own purpose ?
Please explain DMA cycle stealing mode with a timeline diagram.Does the DMA wait for 1 byte before aquiring the bus control and is this the same time when CPU utilizes th...
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