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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2024-1} & \textbf{2024-2} & \textbf{2023} &  \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 2&2&2& 3 &1&2&1&2&3
\\\hline\textbf{2 Marks Count} & 3&3&4& 2 &2&2&2&2.67&4
\\\hline\textbf{Total Marks} & 8&8&10& 7 &5&6&\bf{5}&\bf{7.33}&\bf{10}\\\hline
\end{array}}}$$

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#2901
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UGC NET CSE | December 2011 | Part 2 | Question: 32
A chip having $150$ gates will be classified asSSIMSILSIVLSI
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#2902
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UGC NET CSE | December 2011 | Part 2 | Question: 31
CPU does not perform the operationData transferLogic operationArithmetic operationAll of the above
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#2903
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6 votes
Pipelining
Consider a 4 stage pipeline where the branch is resolved at the end of the second cycle for unconditional branches and at the end of the third cycle for the conditional branches. Assume that no ... b)0.459 c)0.689 d)1.45
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#2904
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Pipelining
You are given a non-pipelined processor design which has a cycle time of 10ns and average CPI(cycle per instruction) of 1.4.The designers ... cycles(these occurrences are disjoint).what is speedup compared to the original processor?
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#2905
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UGC NET CSE | June 2016 | Part 2 | Question: 48
Pipelining improves performance bydecreasing instruction latencyeliminating data hazardsexploiting instruction level parallelismdecreasing the cache miss rate
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#2906
671
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1 answers
1 votes
co - memory interface query,whether to do or not
Do we need to practise memory interfacing (not given in syllabus) questions? but people are actively answering questions here on memory interface. If yes, what types might come?
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#2907
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3 votes
2s complement
2s complement of - 539 is 539 so in her it is 21B should be the answer
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#2908
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5 votes
Cache Hardware Organisation
What is the role of a Multiplexor in Fully Associative, k-way set associative Cache organisation?The way I look at it, we need |blocks_in_cache| no. ... comparators and then determine which comparator has shown the match/no match at all?
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#2909
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1 votes
#co
Can we implement nested function calls and recursive calls without stack ??
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#2910
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3 answers
11 votes
Cycle Stealing(DMA)
In Cycle Stealing, does the DMA interrupt the processor everytime, or it uses the cycle while the processor remains unknown of the fact?
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#2911
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UGC NET CSE | December 2015 | Part 3 | Question: 6
A CPU handles interrupt by executing interrput service subroutine ____by checking interrupt register after execution of each instructionby checking ... interrupt is registeredby checking interrupt register at regular time interval
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#2912
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UGC NET CSE | December 2015 | Part 3 | Question: 5
A DMA controller transfers 32-bit words to memory using cycle Stealing. The words are assembled from a device that transmits characters at a rate of 4800 characters ... the CPU be slowed down because of the DMA transfer?0.06%0.12%1.2%2.5%
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#2913
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UGC NET CSE | December 2015 | Part 3 | Question: 2
What will be the output at $\text{PORT1 }$if the following program is executed?MVI B, 82H MOV A, B MOV C, A MVI D, 37H OUT PORT1 HLT$37H$82H$B9H$00H$
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#2914
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Cache
Wide cache is available so in my program which data structure I can use? 1.Array2.Linked list
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#2915
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how to find number of multiplexer in direct mapping..
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#2916
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Cache memory access time
If the question is given, L1 cache access time is 150ns/word and one block of L1 cache contains 5words.Should I multiply the access time by 5 or leave it at 150ns as memory is word addressable?
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#2917
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A processor has a 16 bit data bus and 32 bit address bus, what is the maximum byte locations it can address
A processor has a 16 bit data bus and 32 bit address bus, what is the maximum byte locations it can address
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#2918
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2 answers
1 votes
Number System
What is 16's Complement of (-48)base10 ??
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#2919
692
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1 answers
2 votes
CO
The cache memory of 1K words uses direct mapping with a block size of 4 words. How many blocks can the cache256512 words.1024 words128 words
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#2920
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1 answers
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Microprocessor UGCNET
A computer with $32$ bit wide data bus user $4k \times 8$ static RAM memory chips. The smallest memory this computer can have is...?$32$kb$16$kb$8$KB$24$kb
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