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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2024-1} & \textbf{2024-2} & \textbf{2023} &  \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 2&2&2& 3 &1&2&1&2&3
\\\hline\textbf{2 Marks Count} & 3&3&4& 2 &2&2&2&2.67&4
\\\hline\textbf{Total Marks} & 8&8&10& 7 &5&6&\bf{5}&\bf{7.33}&\bf{10}\\\hline
\end{array}}}$$

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#2921
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Microprocessor UGCNET
A computer with $32$ bit wide data bus user $4k \times 8$ static RAM memory chips. The smallest memory this computer can have is...?$32$kb$16$kb$8$KB$24$kb
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#2922
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0 answers
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GATE 2016-2-30
Can anyone draw the pipeline diagram for this question?https://gateoverflow.in/39627/gate-2016-2-30
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#2923
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UGC NET CSE | Junet 2015 | Part 3 | Question: 5
The CPU of a system having 1 MIPS execution rate needs 4 machine cycles on an average for executing an instruction. The fifty percent of the cycles use ... transfer technique is used?500 Kbytes/sec2.2 Mbytes/sec125 Kbytes/sec250 Kbytes/sec
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#2924
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UGC NET CSE | Junet 2015 | Part 3 | Question: 3
The RST 7 instruction in 8085 microprocessor is equal toCALL 0010 HCALL 0034 HCALL 0038 HCALL 003C H
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#2925
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UGC NET CSE | Junet 2015 | Part 3 | Question: 2
Consider a 32-bit microprocessor, with a 16-bit external data bus, driven by an 8 MHz input clock. Assume that this microprocessor has a bus cycle whose minimum duration ... bytes/sec$16 \times 10^6$ bytes/sec$4 \times 10^9$ bytes/sec
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#2926
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UGC NET CSE | Junet 2015 | Part 2 | Question: 46
In the case of parallelization, Amdahl's law states that if $P$ is the proportion of a program that can be made parallel and $(1-P)$ is the proportion that cannot be parallelized, then ... P)+\frac{P}{N}} \\$\dfrac{1}{P+\frac{(1-P)}{N}}$
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#2927
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UGC NET CSE | Junet 2015 | Part 2 | Question: 31
Match the following: ... $a-iv, b-iii, c-ii, d-ii$
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#2928
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ADD X,Y which addressing mode
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#2929
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5 votes
UGC NET CSE | December 2013 | Part 3 | Question: 50
Which of the following is a design criteria for instruction formats?The size of instructionsThe number of bits in the address fieldsThe sufficient space in the instruction format to express all the operands desiredAll of these
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#2930
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1 answers
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UGC NET CSE | December 2013 | Part 3 | Question: 49
Match the following: ... $\text{a-iii, b-i, c-iv, d-ii}$
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#2931
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Booth vs Add&SHIFT Calculation?
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#2932
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Ace Test Series: CO & Architecture - Cache Memory
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#2933
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Self Made: Hit Latency
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#2934
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UGC NET CSE | December 2014 | Part 3 | Question: 06
Specify the contents of the accumulator and the status of the $S, Z$ and $CY$ flags when $8085$ microprocessor performs addition of $87 H$ and $79 H$. $11, 1, 1, 1$10, 0, 1, 0$01, 1, 0, 0$00, 0, 1, 1$
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#2935
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2 answers
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UGC NET CSE | December 2014 | Part 3 | Question: 05
How many times will the following loop be executed ? LXI B, 0007 HLOP : DCX B MOV A, B ORA C JNZ LOP $05$ $07$ $09$00$
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#2936
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UGC NET CSE | December 2014 | Part 3 | Question: 04
Match the following $8085$ instructions with the flags $:$\begin{array}{} {} & {\textbf{List - I}} & {} & {\textbf{List - II}} \\ \text{a.} & \text{XCHG} & \text{i.} & ... $\text{a-ii, b-iv, c-i, d-iii}$
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#2937
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2 answers
4 votes
UGC NET CSE | December 2014 | Part 3 | Question: 01
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#2938
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1 answers
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UGC NET CSE | September 2013 | Part 3 | Question: 33
The instruction : MOV CL, [BX] [DI] + 8 represents the ____ addressing modeBased RelativeBased IndexedIndexed RelativeRegister Indexed
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#2939
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1 answers
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UGC NET CSE | September 2013 | Part 3 | Question: 32
A given memory chip has 14 address and 8 data pins. It has the following number of locations.$2^8$2^{14}$2^6$2^{12}$
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#2940
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UGC NET CSE | September 2013 | Part 3 | Question: 31
Which of the following electronic component is not found in IC’s?DiodeResistorTransistorInductor
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