Recent questions tagged cache-memory / GATE Overflow for GATE CSE

0 votes

0 answers

331

Cache Memory Doubt
What is the main reason behind using Cache Mapping?Suppose if there is a cache hit, then will mapping be of any use?

What is the main reason behind using Cache Mapping?Suppose if there is a cache hit, then will mapping be of any use?

Devshree Dubey

243 views

Devshree Dubey asked Aug 1, 2018

0 votes

0 answers

332

Computer Orgranization (Conceptual Question)
When the WRITE THROUGH protocol is implemented in a simultaneous Access memory Organization then hit ratio of write operation becomes 1. Then why not the read hit also become 1 as now the data is available in all level ?

When the WRITE THROUGH protocol is implemented in a simultaneous Access memory Organization then hit ratio of write operation becomes 1. Then why not the read hit also be...

Ashish Roy 1

142 views

Ashish Roy 1 asked Jul 30, 2018

0 votes

0 answers

333

Misses
Consider the system have L1 data cache with 50 percent of hit rate and take 2 cycles when hit in L1 cache, L2 cache with 70% of hit rate and take 15 cycles when hit in L2 cache and main memory with 100% of hit rate and 200 cycles when hit in main memory to access a block. If main memory speed is improved 15%, then the improvement in L1 miss time is ________. (upto 2 decimal place)

Consider the system have L1 data cache with 50 percent of hit rate and take 2 cycles when hit in L1 cache, L2 cache with 70% of hit rate and take 15 cycles when hit in L2...

Na462

537 views

Na462 asked Jul 29, 2018

0 votes

1 answer

334

No. of Misses
Assume that we have a two dimensional array of 60 × 60. Each element is of 4 bytes and array is stored in row major order. RAM is 2 MB and cache is 8 KB with each block of 16 bytes. In case of direct mapped cache, the number of cache misses are _______ (Assume that cache is empty initially). Ans. 1288

Assume that we have a two dimensional array of 60 × 60. Each element is of 4 bytes and array is stored in row major order. RAM is 2 MB and cache is 8 KB with each block ...

Na462

893 views

Na462 asked Jul 29, 2018

0 votes

0 answers

335

Finding cache size for virtually indexed physically addressed cache

eswaraleti143

231 views

eswaraleti143 asked Jul 28, 2018

1 votes

1 answer

336

Miss Penalty
Why we need to calculate miss penalty? I mean in miss rate we get every information about page table and valid/invalid bit. So, still why we calculating miss penalty? got some information here and here Still I want to know, if only error calculation done by miss penalty?

Why we need to calculate miss penalty? I mean in miss rate we get every information about page table and valid/invalid bit. So, still why we calculating miss penalty?got ...

srestha

2.2k views

srestha asked Jul 25, 2018

1 votes

1 answer

337

Cache System
In a direct cache controller each main memory address can be viewed as consisting of three fields. The least significant bits identify a unique word/byte within a block. The cache logic interprets the remaining s' bits as a tag of (s - r) bits (most significant portion) ... What is the size of main memory and cache memory respectively. Ans. 2^(s+w) bytes/word and 2^(r+w) bytes/word

In a direct cache controller each main memory address can be viewed as consisting of three fields. The least significant bits identify a unique word/byte within a block....

Na462

594 views

Na462 asked Jul 25, 2018

2 votes

2 answers

338

Cache Memory
Consider the following statements: S1 : Doubling the line size halves the number of tags in the cache. S2 : Doubling the associativity doubles the number of tags in the cache. S3 : Doubling the line size usually reduce compulsory misses. Which of the above statements is always true?

Consider the following statements:S1 : Doubling the line size halves the number of tags in the cache.S2 : Doubling the associativity doubles the number of tags in the cac...

Na462

2.2k views

Na462 asked Jul 23, 2018

0 votes

1 answer

339

Cache Memory
Suppose after analyzing a new cache design, you discover that the cache has too many conflict misses and this needs to be resolved. You know that you must increase associativity in order to decrease the number of cache misses. What are the implications of increasing associativity? A. Slower cache access time B. Increase index bits C. Increase block size D. All of these

Suppose after analyzing a new cache design, you discover that the cache has too many conflict misses and this needs to be resolved. You know that you must increase associ...

Na462

1.3k views

Na462 asked Jul 23, 2018

1 votes

1 answer

340

Hennessy and Patterson
Assume that we have three scenarios - is a fully associative cache, is a two way set associative cache and is a direct mapped cache. The cache size is 256 bytes. T The cache line size is 8 bytes. All variables are 4 bytes. Assume we have separate instruction and data caches.Assumption -- assign a[1024] ... { 2.b += q*a[64*i]; 3.} 4.for(i=0;i<16;i++){ 5.c += r*a[64*i]; 6.}

Assume that we have three scenarios - is a fully associative cache, is a two way set associative cache and is a direct mapped cache. The cache size is 256 bytes. TThe cac...

Bhavna

702 views

Bhavna asked Jul 19, 2018

0 votes

0 answers

341

Virtual Memory Access Time
Avg. virtual address access time = avg address translation time+avg. memory access time Why do we need address translation time separately?(otherwise we do TLB access, then cache access then MM access) Avg address translation time=TLB access time+page table access ... question is if TLB hit is taking then why do we take cache hit? We take cache hit, when TLB miss right?

Avg. virtual address access time = avg address translation time+avg. memory access timeWhy do we need address translation time separately?(otherwise we do TLB access, the...

srestha

244 views

srestha asked Jul 18, 2018

0 votes

2 answers

342

UGC NET CSE | July 2018 | Part 2 | Question: 98
Which of the following mapping is not used for mapping process in cache memory Associative mapping Direct mapping Set-Associative mapping Segmented - page mapping

Which of the following mapping is not used for mapping process in cache memoryAssociative mappingDirect mappingSet-Associative mappingSegmented - page mapping

Pooja Khatri

12.1k views

Pooja Khatri asked Jul 13, 2018

0 votes

0 answers

343

Cache Memory
Hi sir, i want to ask that how we'll come to know whether this is an independent memory organization or it is a hierarchical organization ? In case of hierarchical it's answer would've been 1.23T1 In case of independent it's answer is 1.11T1

Hi sir, i want to ask that how we'll come to know whether this is an independent memory organization or it is a hierarchical organization ? In case of hierarchical it's a...

Priyansh Singh

284 views

Priyansh Singh asked Jul 2, 2018

–1 votes

1 answer

344

Carl Hamacher Cache Memory
What should be correct answer to this question? In solution it's option A in Carl hamacher text book it's B ? I am confused please help

What should be correct answer to this question?In solution it's option A in Carl hamacher text book it's B ? I am confused please help

vupadhayayx86

925 views

vupadhayayx86 asked Jun 13, 2018

0 votes

1 answer

345

Cache memory
Consider a scenario, where there is 2 level cache in a memory hierarchy. 1)Now here if we take 1.4 memory accesses per instruction, that means if there are 100 instructions, then there will be 140 memory accesses. Here my question is how memory accesses can ... What miss rate is for L1,L2 and total in this memory hierarchy? Is it not number of misses in total number of instructions?

Consider a scenario, where there is 2 level cache in a memory hierarchy.1)Now here if we take 1.4 memory accesses per instruction, that means if there are 100 instruction...

srestha

694 views

srestha asked Jun 10, 2018

0 votes

1 answer

346

Computer organisation
If cache access time is $100ns$, main memory access time is $1000ns$ and the hit ratio is $0.9$. Find the average access time and also define hit ratio.

If cache access time is $100ns$, main memory access time is $1000ns$ and the hit ratio is $0.9$. Find the average access time and also define hit ratio.

Shivani gaikawad

542 views

Shivani gaikawad asked May 24, 2018

0 votes

0 answers

347

Cache coloring
I am stuck in two doubts. Is page-coloring / cache-coloring same as set-associative mapping in cache ( that is are they different names for same concept)? Is the cache line size always equal to the page-size, or it depends upon implementation details ( that is it will be given in the question )?

I am stuck in two doubts.Is page-coloring / cache-coloring same as set-associative mapping in cache ( that is are they different names for same concept)?Is the cache line...

Harsh Kumar

403 views

Harsh Kumar asked May 13, 2018

0 votes

1 answer

348

Cache Coherence
A system with 2 cores $C0$ and $C1$ uses Write–invalidate Snoopy cache coherency protocol with $Valid$, $Dirty$ and $Shared$ bits. A program runs on the system where $C0$ writes to $A$ and afterwards $C1$ reads from $A$. This happens for 1000 times. Find number of times system bus is used by the program..

A system with 2 cores $C0$ and $C1$ uses Write–invalidate Snoopy cache coherency protocol with $Valid$, $Dirty$ and $Shared$ bits. A program runs on the system where $C...

habedo007

800 views

habedo007 asked May 7, 2018

2 votes

2 answers

349

ISRO2018-73
For a multi-processor architecture, in which protocol a write transaction is forwarded to only those processors that are known to possess a copy of newly altered cache line? Snoopy bus protocol Cache coherency protocol Directory based protocol None of the above

For a multi-processor architecture, in which protocol a write transaction is forwarded to only those processors that are known to possess a copy of newly altered cache li...

Arjun

4.2k views

Arjun asked Apr 22, 2018

0 votes

0 answers

350

caching and virtual memory
I am having troble with these following questions. Please I need help

I am having troble with these following questions. Please I need help

Samson Bankole

381 views

Samson Bankole asked Apr 19, 2018

1 votes

0 answers

351

#sample_test_iitk
An address sequence S experiences 100 compulsory cache misses. The sequence S experiences 500 misses when it is passed through a 32 KB fully-associative cache. The sequence S experiences 1000 misses when it is passed through a 32 KB 8-way set- ... conflict misses that the sequence S experiences when it is passed through a 32 KB 8-way set-associative cache is ___________

An address sequence S experiences 100 compulsory cache misses. The sequence S experiences 500 misses when it is passed through a 32 KB fully-associative cache. The sequen...

tapzo

749 views

tapzo asked Apr 15, 2018

3 votes

1 answer

352

computer organization
Consider two cache organizations. The first one if $64 \text{ KB}$ way associative with $64\text{ byte}$ block size. The second one is of the $64 \text{ KB}$ direct mapped cache. The size of an address is $32\text{bits}$ in both ... between the hit latencies of both cache organizations (i.e. associative hit latency - direct mapped hit latency) (in nsec) is ________ .

Consider two cache organizations. The first one if $64 \text{ KB}$ way associative with $64\text{ byte}$ block size. The second one is of the $64 \text{ KB}$ direct mappe...

Prince Sindhiya

669 views

Prince Sindhiya asked Apr 6, 2018

0 votes

1 answer

353

Hit Ratio and miss ratio question
In some problems we multiply only with the second part of the equation with (1-H1) component and leave the first part. Whereas in other cases we multiply with cache hit and miss. Is there any patterns for this or could be explained.

In some problems we multiply only with the second part of the equation with (1-H1) component and leave the first part. Whereas in other cases we multiply with cache hit a...

nirupama thakur

2.0k views

nirupama thakur asked Mar 17, 2018

0 votes

0 answers

354

Heirechical Cache
In Question : https://gateoverflow.in/584/gate1992-5-a We have used heireichal cache then: Average memory access time = 0.8 * Time spent for read + 0.2 * Time spent for write ----- > OK but Time spent for read :- 0.9 ⨯ 50 + 0.1 ⨯ (500+50) ??? ... 500 + 0.1 ⨯ 500 ??? Its a write through policy so wont it be Tavg = 500?(Because we update both cache and memory at the same time)

In Question : https://gateoverflow.in/584/gate1992-5-a We have used heireichal cache then:Average memory access time = 0.8 * Time spent for read + 0.2 * Time spent for w...

Na462

409 views

Na462 asked Mar 16, 2018

1 votes

1 answer

355

#1 Testbook Mock Test (COA - Cache Memory)
Suppose that in $500$ memory references there are $50$ misses in the first level cache and $20$ misses in the second level cache. Assume miss penalty from the $L2$ cache to memory in $100$ cycles. The hit time of $L2$ cache is $20$ ... $10$ $5$ $15$ $\text{None of these}$

Suppose that in $500$ memory references there are $50$ misses in the first level cache and $20$ misses in the second level cache. Assume miss penalty from the $L2$ cache ...

rfzahid

496 views

rfzahid asked Mar 15, 2018

0 votes

1 answer

356

Cache Organization
Ques. In a two-level memory hierarchy, let $t_1 = 10^{-7s}$ and $t_2 = 10^{-2s}$. If ta denotes the average access time of the memory hierarchy, and if we define the access efficiency to be equal to $t_1=t_a$, then what must the hit ratio $H$ ... Why they have considered only Hit Time instead of Hit Ratio and Hit time.... and plz explain which one to use and when...

Ques. In a two-level memory hierarchy, let $t_1 = 10^{-7s}$ and $t_2 = 10^{-2s}$. If ta denotes the average accesstime of the memory hierarchy, and if we define the acces...

Na462

487 views

Na462 asked Mar 9, 2018

1 votes

1 answer

357

Cache Organization
My Doubt is simple How to know which cache organization to use hierarchical or direct cache while calculating the average access time. Like in this Question:- https://gateoverflow.in/2308/gate1993-11 Here hierarchal access is used and why? Plz help me

My Doubt is simple How to know which cache organization to use hierarchical or direct cache while calculating the averageaccess time.Like in this Question:- https://gateo...

Na462

367 views

Na462 asked Mar 8, 2018

0 votes

1 answer

358

Cache-Memory
If it takes 50ns to search associative registers and also about 100ns to get access to main memory then find out the % of slowdown in memory access time?(Given hit ratio 90%)- A)60 B)75 C)20 D)90

If it takes 50ns to search associative registers and also about 100ns to get access to main memory then find out the % of slowdown in memory access time?(Given hit ratio ...

satendra

1.3k views

satendra asked Mar 3, 2018

1 votes

0 answers

359

IITG Quiz
Consider a computer system based on 32 bit processor with 8KB direct mapped on-chip I-cache and 16KB 2-way set associative on-chip D-cache. The off-chip unified cache is 128 KB 4-way set associative. Block size for on-chip cache is 8 words and ... 275(all in decimal). Assuming caches are initially empty, indicate the non-empty blocks on all the caches after execution of the instruction.

Consider a computer system based on 32 bit processor with 8KB direct mapped on-chip I-cache and 16KB 2-way set associative on-chip D-cache. The off-chip unified cache is ...

Samujjal Das

610 views

Samujjal Das asked Feb 16, 2018

45 votes

9 answers

360

GATE CSE 2018 | Question: 34
The size of the physical address space of a processor is $2^P$ bytes. The word length is $2^W$ bytes. The capacity of cache memory is $2^N$ bytes. The size of each cache block is $2^M$ words. For a $K$-way set-associative cache memory, the length (in number of bits) of the tag field is $P-N- \log_2K$ $P-N+ \log_2 K$ $P-N-M-W- \log_2 K$ $P-N-M-W+ \log_2 K$

The size of the physical address space of a processor is $2^P$ bytes. The word length is $2^W$ bytes. The capacity of cache memory is $2^N$ bytes. The size of each cache ...

gatecse

12.0k views

gatecse asked Feb 14, 2018

tags	tag:apple
author	user:martin
title	title:apple
content	content:apple
exclude	-tag:apple
force match	+apple
views	views:100
score	score:10
answers	answers:2
is accepted	isaccepted:true
is closed	isclosed:true

Slides