Register

Web Page

Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2024-1} & \textbf{2024-2} & \textbf{2023} &  \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 2&2&2& 3 &1&2&1&2&3
\\\hline\textbf{2 Marks Count} & 3&3&4& 2 &2&2&2&2.67&4
\\\hline\textbf{Total Marks} & 8&8&10& 7 &5&6&\bf{5}&\bf{7.33}&\bf{10}\\\hline
\end{array}}}$$

Filter

Recent questions in CO and Architecture

1 votes
0 answers
3321
clock cycle
the maximum clock frequency at which the data path can operate is ??
the maximum clock frequency at which the data path can operate is ??
User Avatar
3 votes
1 answer
3322
reducing misses in cache..
which of the following statement (if any) are generally true? 1. There is no way to reduce compulsory misses. 2. Full associative cache have no conflict misses. 3. In reducing misses, associativity is more important than capacity.
which of the following statement (if any) are generally true?1. There is no way to reduce compulsory misses.2. Full associative cache have no conflict misses.3. In reduci...
User Avatar
1 votes
3 answers
3325
What is Byte Addressable and Word Addressable means in computer Architecture ? Difference between them with examples?
What is Byte Addressable and Word Addressable means in computer Architecture ? Difference between them with examples?I also find some sources like stack overflow and wik...
User Avatar
1 votes
3 answers
3328
Single accumulator organisation
The size of the instruction in a single accumulator is 16 bits. In order to evaluate the expression Y = A-B+C / E+F , how much memory space is required to store the program? a) 18 bytes b)24 bytes c)22 bytes d)20 bytes
The size of the instruction in a single accumulator is 16 bits. In order to evaluate the expression Y = A-B+C / E+F , how much memory space is required to store the progr...
User Avatar
2 votes
1 answer
3332
associative cache
Consider a 32 bit processor that has an on chip 16Kbyte 4 way set associative cache. assume that cache has a size of four 32 bit words. the set no in the cache to which the word from memory location FFFAE8FA is mapped_________
Consider a 32 bit processor that has an on chip 16Kbyte 4 way set associative cache. assume that cache has a size of four 32 bit words. the set no in the cache to which ...
User Avatar
3 votes
0 answers
3336
Differencee Between DCR and DCRL Instruction.
Want to know difference between : DCR and DCRL SUB and SUBL
Want to know difference between :DCR and DCRLSUB and SUBL
User Avatar
5 votes
1 answer
3338
RISC processor window size
Assume that RISC processor contains 10 global registers, 10 local registers, 6 In register and 6 Out register. It contain 4 register windows what is the size of window and register file of the processor? a) 30 and 74 b) 32 and 74 c) 22 and 64 d) 22 and 70
Assume that RISC processor contains 10 global registers, 10 local registers, 6 In register and 6 Out register. It contain 4 register windows what is the size of window an...
User Avatar
Page: