Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2024-1} & \textbf{2024-2} & \textbf{2023} & \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 2&2&2& 3 &1&2&1&2&3
\\\hline\textbf{2 Marks Count} & 3&3&4& 2 &2&2&2&2.67&4
\\\hline\textbf{Total Marks} & 8&8&10& 7 &5&6&\bf{5}&\bf{7.33}&\bf{10}\\\hline
\end{array}}}$$

Recent questions in CO and Architecture

0 votes

0 answers

3581

GATE CSE 1994 | Question: 10

Kathleen

491 views

Kathleen asked Oct 5, 2014

22 votes

2 answers

3582

GATE CSE 1994 | Question: 3.2
State True or False with one line explanation Expanding opcode instruction formats are commonly employed in RISC. (Reduced Instruction Set Computers) machines.

State True or False with one line explanationExpanding opcode instruction formats are commonly employed in RISC. (Reduced Instruction Set Computers) machines.

Kathleen

4.8k views

Kathleen asked Oct 4, 2014

0 votes

0 answers

3583

GATE CSE 1994 | Question: 3.1

Kathleen

690 views

Kathleen asked Oct 4, 2014

80 votes

8 answers

3584

GATE CSE 2010 | Question: 48
A computer system has an $L1$ cache, an $L2$ cache, and a main memory unit connected as shown below. The block size in $L1$ cache is $4$ words. The block size in $L2$ cache is $16$ words. The memory access times are $2$ ... $L1$ cache. What is the time taken for this transfer? $2$ nanoseconds $20$ nanoseconds $22$ nanoseconds $88$ nanoseconds

A computer system has an $L1$ cache, an $L2$ cache, and a main memory unit connected as shown below. The block size in $L1$ cache is $4$ words. The block size in $L2$ cac...

go_editor

43.0k views

go_editor asked Sep 30, 2014

0 votes

0 answers

3585

GATE CSE 1993 | Question: 20

Kathleen

581 views

Kathleen asked Sep 29, 2014

49 votes

6 answers

3586

GATE CSE 1993 | Question: 11
In the three-level memory hierarchy shown in the following table, $p_i$ denotes the probability that an access request will refer to $M_i$ ... a page swap is $T_i$. Calculate the average time $t_A$ required for a processor to read one word from this memory system.

In the three-level memory hierarchy shown in the following table, $p_i$ denotes the probability that an access request will refer to $M_i$.$$\begin{array}{|c|c|c|c|} \hli...

Kathleen

11.2k views

Kathleen asked Sep 29, 2014

31 votes

3 answers

3587

GATE CSE 1993 | Question: 10
The instruction format of a CPU is: $\text{Mode}$ and $\text{RegR}$ together specify the operand. $\text{RegR}$ specifies a CPU register and $\text{Mode}$ specifies an addressing mode. In particular, $\text{Mode}=2$ specifies that ... address of the operand? Assuming that is a non-jump instruction, what are the contents of PC after the execution of this instruction?

The instruction format of a CPU is:$\text{Mode}$ and $\text{RegR}$ together specify the operand. $\text{RegR}$ specifies a CPU register and $\text{Mode}$ specifies an add...

Kathleen

7.2k views

Kathleen asked Sep 29, 2014

35 votes

3 answers

3588

GATE CSE 1997 | Question: 5.3
A micro instruction is to be designed to specify: none or one of the three micro operations of one kind and none or upto six micro operations of another kind The minimum number of bits in the micro-instruction is: $9$ $5$ $8$ None of the above

A micro instruction is to be designed to specify:none or one of the three micro operations of one kind andnone or upto six micro operations of another kindThe minimum num...

Kathleen

11.6k views

Kathleen asked Sep 29, 2014

3 votes

1 answer

3589

GATE CSE 1997 | Question: 5.2
Contents of A register after the execution of the following 8085 microprocessor program is MVIA, 55 H MVI C, 25 H ADDC DAA 7AH 80H 50H 22H

Contents of A register after the execution of the following 8085 microprocessor program is MVIA, 55 H MVI C, 25 H ADDC DAA 7AH80H50H22H

Kathleen

6.2k views

Kathleen asked Sep 29, 2014

16 votes

3 answers

3590

GATE CSE 1997 | Question: 2.4
The correct matching for the following pairs is: ... $A-2\quad B-1\quad C-3\quad D-4$ $A-4\quad B-3\quad C-2\quad D-1$ $A-2\quad B-3\quad C-4\quad D-1$

The correct matching for the following pairs is:$$\begin{array}{ll} \text{(A) DMA I/O} & \text{(1) High speed RAM} \\ \text{(B) Cache} & \text{(2) Disk} \\ \text{(C) I...

Kathleen

7.7k views

Kathleen asked Sep 29, 2014

1 votes

1 answer

3591

GATE CSE 1997 | Question: 2.2
RST 7.5 interrupt in 8085 microprocessor executes the interrupt service routing from interrupt vector location 0000H 0075H 003CH 0034H

RST 7.5 interrupt in 8085 microprocessor executes the interrupt service routing from interrupt vector location0000H0075H003CH0034H

Kathleen

3.0k views

Kathleen asked Sep 29, 2014

47 votes

3 answers

3592

GATE CSE 2010 | Question: 33
A $5-$stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take $1$ clock cycle each for any instruction. The PO stage takes $1$ clock cycle for ... $13$ $15$ $17$ $19$

A $5-$stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID,...

go_editor

22.4k views

go_editor asked Sep 29, 2014

33 votes

2 answers

3593

GATE CSE 2012 | Question: 54
A computer has a $256\text{-KByte}$, 4-way set associative, write back data cache with block size of $32\text{-Bytes}$. The processor sends $32\text{-bit}$ ... bit and $1$ replacement bit. The number of bits in the tag field of an address is $11$ $14$ $16$ $27$

A computer has a $256\text{-KByte}$, 4-way set associative, write back data cache with block size of $32\text{-Bytes}$. The processor sends $32\text{-bit}$ addresses to t...

gatecse

22.4k views

gatecse asked Sep 29, 2014

32 votes

3 answers

3594

GATE CSE 2011 | Question: 43
An $8\text{KB}$ direct-mapped write-back cache is organized as multiple blocks, each size of $32\text{-bytes}$. The processor generates $32\text{-bit}$ addresses. The cache controller contains the tag information for each cache block comprising of the ... the cache controller to store meta-data (tags) for the cache? $4864$ bits $6144$ bits $6656$ bits $5376$ bits

An $8\text{KB}$ direct-mapped write-back cache is organized as multiple blocks, each size of $32\text{-bytes}$. The processor generates $32\text{-bit}$ addresses. The cac...

go_editor

12.5k views

go_editor asked Sep 29, 2014

42 votes

2 answers

3595

GATE CSE 2011 | Question: 41
Consider an instruction pipeline with four stages $\text{(S1, S2, S3 and S4)}$ each with combinational circuit only. The pipeline registers are required between each stage and at the end of the last stage. Delays for the stages and for the pipeline ... under ideal conditions when compared to the corresponding non-pipeline implementation? $4.0$ $2.5$ $1.1$ $3.0$

Consider an instruction pipeline with four stages $\text{(S1, S2, S3 and S4)}$ each with combinational circuit only. The pipeline registers are required between each stag...

go_editor

13.8k views

go_editor asked Sep 29, 2014

50 votes

1 answer

3596

GATE CSE 2011 | Question: 28
On a non-pipelined sequential processor, a program segment, which is the part of the interrupt service routine, is given to transfer $500$ bytes from an I/O device to memory. Initialize the address register Initialize the count to 500 LOOP: Load a byte from device Store ... is used in a place of the interrupt driven program based input-output? $3.4$ $4.4$ $5.1$ $6.7$

On a non-pipelined sequential processor, a program segment, which is the part of the interrupt service routine, is given to transfer $500$ bytes from an I/O device to mem...

go_editor

15.8k views

go_editor asked Sep 29, 2014

48 votes

5 answers

3597

GATE CSE 2011 | Question: 21
Consider a hypothetical processor with an instruction of type $\text{LW R1, 20(R2)}$, which during execution reads a $32\text{-bit}$ word from memory and stores it in a $32\text{-bit}$ ... mode implemented by this instruction for the operand in memory? Immediate addressing Register addressing Register Indirect Scaled Addressing Base Indexed Addressing

Consider a hypothetical processor with an instruction of type $\text{LW R1, 20(R2)}$, which during execution reads a $32\text{-bit}$ word from memory and stores it in a ...

go_editor

17.7k views

go_editor asked Sep 29, 2014

69 votes

6 answers

3598

GATE CSE 2014 Set 3 | Question: 44
The memory access time is $1$ nanosecond for a read operation with a hit in cache, $5$ nanoseconds for a read operation with a miss in cache, $2$ nanoseconds for a write operation with a hit in cache and $10$ nanoseconds for a write ... cache hit-ratio is $0.9$. The average memory access time (in nanoseconds) in executing the sequence of instructions is ______.

The memory access time is $1$ nanosecond for a read operation with a hit in cache, $5$ nanoseconds for a read operation with a miss in cache, $2$ nanoseconds for a write ...

go_editor

24.5k views

go_editor asked Sep 28, 2014

53 votes

7 answers

3599

GATE CSE 2014 Set 3 | Question: 43
An instruction pipeline has five stages, namely, instruction fetch (IF), instruction decode and register fetch (ID/RF), instruction execution (EX), memory access (MEM), and register writeback (WB) with stage latencies $1$ ns, $2.2 $ ns, $2$ ... program on the old and the new design are $P$ and $Q$ nanoseconds, respectively. The value of $P/Q$ is __________.

An instruction pipeline has five stages, namely, instruction fetch (IF), instruction decode and register fetch (ID/RF), instruction execution (EX), memory access (MEM), a...

go_editor

22.6k views

go_editor asked Sep 28, 2014

31 votes

4 answers

3600

GATE CSE 2014 Set 3 | Question: 9
Consider the following processors (ns stands for nanoseconds). Assume that the pipeline registers have zero latency. $\text{P1:}$ Four-stage pipeline with stage latencies $\text{1 ns, 2 ns, 2 ns, 1 ns}$. $\text{P2:}$ Four-stage pipeline with stage latencies ... $\text{P1}$ $\text{P2}$ $\text{P3}$ $\text{P4}$

Consider the following processors (ns stands for nanoseconds). Assume that the pipeline registers have zero latency. $\text{P1:}$ Four-stage pipeline with stage latencies...

go_editor

8.4k views

go_editor asked Sep 28, 2014

Page:

« prev
1
...
175
176
177
178
179
180
181
182
183
184
185
...
199
next »

tags	tag:apple
author	user:martin
title	title:apple
content	content:apple
exclude	-tag:apple
force match	+apple
views	views:100
score	score:10
answers	answers:2
is accepted	isaccepted:true
is closed	isclosed:true