Register

Web Page

Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2024-1} & \textbf{2024-2} & \textbf{2023} &  \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 2&2&2& 3 &1&2&1&2&3
\\\hline\textbf{2 Marks Count} & 3&3&4& 2 &2&2&2&2.67&4
\\\hline\textbf{Total Marks} & 8&8&10& 7 &5&6&\bf{5}&\bf{7.33}&\bf{10}\\\hline
\end{array}}}$$

Filter

Most viewed questions in CO and Architecture

#61
19.9k
views
1 answers
3 votes
Effective Address Calculation
Plz discuss every part with detailed solution with diagram .
User Avatar
#62
19.9k
views
1 answers
1 votes
Morris Mano Numerical [ Important]
A digital computer has a common bus system for 16 registers of 32 bits each. The bus is constructedwith multiplexers.[i] How many selection inputs are there in each multi...
User Avatar
#63
19.9k
views
4 answers
59 votes
GATE CSE 2004 | Question: 64
Consider the following program segment for a hypothetical CPU having three user registers $R_1, R_2$ and $R_3.$\begin{array}{|l|l|c|} \hline \text {Instruction} & \text...
User Avatar
#64
19.9k
views
5 answers
51 votes
GATE CSE 2005 | Question: 69
A device with data transfer rate $10$ KB/sec is connected to a CPU. Data is transferred byte-wise. Let the interrupt overhead be $4\mu$sec. The byte transfer time between...
User Avatar
#65
19.8k
views
1 answers
0 votes
Consider a magnetic disk drive with 8 surfaces, 512 tracks per surface, and 64 sectors per track. Sector size is 1 KB.
Consider a magnetic disk drive with 8 surfaces, 512 tracks per surface, and 64 sectors per track. Sector size is 1 KB.The average seek time is 8 ms, the track-to-track ac...
User Avatar
#66
19.7k
views
3 answers
39 votes
GATE CSE 2008 | Question: 37, ISRO2009-38
The use of multiple register windows with overlap causes a reduction in the number of memory accesses for:Function locals and parametersRegister saves and restoresInstruc...
User Avatar
#67
19.6k
views
7 answers
51 votes
GATE CSE 2008 | Question: 38
In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is:before effective address calculation has starteddur...
User Avatar
#68
19.5k
views
8 answers
76 votes
GATE CSE 2016 Set 2 | Question: 33
Consider a $3 \ \text{GHz}$ (gigahertz) processor with a three stage pipeline and stage latencies $\large\tau_1,\tau_2$ and $\large\tau_3$ such that $\large\tau_1 =\dfrac...
User Avatar
#69
19.5k
views
8 answers
44 votes
GATE CSE 2017 Set 1 | Question: 50
Instruction execution in a processor is divided into $5$ stages, Instruction Fetch (IF), Instruction Decode (ID), Operand fetch (OF), Execute (EX), and Write Back (WB). T...
User Avatar
#70
19.4k
views
11 answers
43 votes
GATE IT 2004 | Question: 50
In an enhancement of a design of a CPU, the speed of a floating point unit has been increased by $\text{20%}$ and the speed of a fixed point unit has been increased by $\...
User Avatar
#71
19.2k
views
4 answers
61 votes
GATE CSE 2008 | Question: 71
Consider a machine with a $2$-way set associative data cache of size $64\text{Kbytes}$ and block size $16\text{bytes}$. The cache is managed using $32\;\text{bit}$ virtua...
User Avatar
#72
19.2k
views
1 answers
4 votes
Draw the space time diagram for a 6-segment pipeline showing the time it takes to process 8 no of tasks.
Draw the space time diagram for a 6-segment pipeline showing the time it takes to process 8 no of tasks.Determine the no of clock cycle that it takes to process 200 tasks...
User Avatar
#73
19.0k
views
6 answers
43 votes
GATE CSE 2016 Set 1 | Question: 31
The size of the data count register of a $\text{DMA}$ controller is $16\;\text{bits}$. The processor needs to transfer a file of $29,154$ kilobytes from disk to main memo...
User Avatar
#74
18.9k
views
3 answers
19 votes
difference between compulsory miss, conflict miss and capacity miss
I want to clearly understand the difference between compulsory miss, conflict miss and capacity misswhat I understood iscompulsory miss: when a block of main memory is tr...
User Avatar
#75
18.7k
views
4 answers
58 votes
GATE CSE 2008 | Question: 33, ISRO2009-80
Which of the following is/are true of the auto-increment addressing mode?It is useful in creating self-relocating codeIf it is included in an Instruction Set Architecture...
User Avatar
#76
18.7k
views
6 answers
49 votes
GATE CSE 2014 Set 1 | Question: 9
A machine has a $32\text{-bit}$ architecture, with $1\text{-word}$ long instructions. It has $64$ registers, each of which is $32$ bits long. It needs to support $45$ ins...
User Avatar
#77
18.4k
views
2 answers
54 votes
GATE CSE 2001 | Question: 12
Consider a $5-$stage pipeline - IF (Instruction Fetch), ID (Instruction Decode and register read), EX (Execute), MEM (memory), and WB (Write Back). All (memory or registe...
User Avatar
#78
18.4k
views
10 answers
43 votes
GATE CSE 2001 | Question: 1.10, UGCNET-Dec2012-III: 36
Suppose a processor does not have any stack pointer registers, which of the following statements is true?It cannot have subroutine call instructionIt cannot have nested s...
User Avatar
#79
18.3k
views
3 answers
64 votes
GATE CSE 2008 | Question: 76
Delayed branching can help in the handling of control hazardsFor all delayed conditional branch instructions, irrespective of whether the condition evaluates to true or f...
User Avatar
#80
18.3k
views
8 answers
23 votes
GATE CSE 2019 | Question: 1
A certain processor uses a fully associative cache of size $16$ kB, The cache block size is $16$ bytes. Assume that the main memory is byte addressable and uses a $32$-bi...
User Avatar
Page: