Login
Register
Dark Mode
Brightness
Profile
Edit Profile
Messages
My favorites
My Updates
Logout
Recent questions tagged addressing-modes
2
votes
1
answer
121
Test by Bikram | Mock GATE | Test 3 | Question: 39
The register $’V’$ contains the value $’500’$. The index register contains the value $’100’$. The address field value of an indexed addressing mode instruction to make it same as a register indirect mode instruction is ___________.
The register $’V’$ contains the value $’500’$. The index register contains the value $’100’$.The address field value of an indexed addressing mode instruction...
Bikram
439
views
Bikram
asked
Feb 9, 2017
GATE
tbb-mockgate-3
numerical-answers
co-and-architecture
addressing-modes
+
–
1
votes
1
answer
122
Test by Bikram | Mock GATE | Test 3 | Question: 17
Relative mode addressing is most relevant to writing a/an __________: Co-routine Position independent code Shareable code Interrupt handler
Relative mode addressing is most relevant to writing a/an __________:Co-routinePosition independent codeShareable codeInterrupt handler
Bikram
267
views
Bikram
asked
Feb 9, 2017
GATE
tbb-mockgate-3
co-and-architecture
addressing-modes
+
–
0
votes
1
answer
123
MadeEasy Subject Test: CO & Architecture - Addressing Modes
vaishali jhalani
355
views
vaishali jhalani
asked
Feb 1, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
addressing-modes
+
–
0
votes
2
answers
124
MadeEasy Subject Test: CO & Architecture - Addressing Modes
Which signed representation has to be taken?
Which signed representation has to be taken?
vaishali jhalani
507
views
vaishali jhalani
asked
Jan 24, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
addressing-modes
+
–
5
votes
2
answers
125
Test by Bikram | Mock GATE | Test 2 | Question: 11
A certain architecture supports indirect, direct, and register addressing modes for use in identifying operands for arithmetic instructions. Which of the following cannot be achieved with a single instruction? Specifying a register number in the ... memory location which in turn contains the value of an operand that will be used by the instruction.
A certain architecture supports indirect, direct, and register addressing modes for use in identifying operands for arithmetic instructions.Which of the following cannot ...
Bikram
604
views
Bikram
asked
Jan 24, 2017
GATE
tbb-mockgate-2
co-and-architecture
addressing-modes
+
–
2
votes
3
answers
126
Testbook Test Series: CO & Architecture - Addressing Modes
Pankaj Joshi
735
views
Pankaj Joshi
asked
Jan 22, 2017
CO and Architecture
testbook-test-series
co-and-architecture
addressing-modes
+
–
0
votes
0
answers
127
difference between registers which hold the address bits and which hold data bits
In CPU, there are two major type of registers:- 1. Registers which hold the address (bits) to access memory cells like program counter, instruction register and MAR etc. 2. Registers which hold the data( bits) of ... mentioned in any book but Best of my knowledge so data mentioned here can be changed if that need to.
In CPU, there are two major type of registers:-1. Registers which hold the address (bits) to access memory cells like program counter, instruction register and MAR etc.2....
khushtak
851
views
khushtak
asked
Jan 19, 2017
CO and Architecture
co-and-architecture
addressing-modes
+
–
1
votes
1
answer
128
ace coa subject test
AFAIK "In direct we do specify the address of the operand right? Its just that we specify it in the instruction directly, ie hardcode the address in the instruction. In implied there is no address given since address is deduced from the operation itself." Is this right?
AFAIK "In direct we do specify the address of the operand right? Its just that we specify it in the instruction directly, ie hardcode the address in the instruction. In i...
Purple
550
views
Purple
asked
Jan 17, 2017
CO and Architecture
test-series
ace-test-series
addressing-modes
+
–
2
votes
1
answer
129
Test by Bikram | Mock GATE | Test 1 | Question: 44
Match the pairs about implementation and addressing modes: Group A Group B A. Array I Indirect Addressing B Relocatable code II Indexed Addressing C Array as parameter III Base Register Addressing ... $(A-III), (B-II), (C-I)$ $(A-I), (B-III), (C-II)$
Match the pairs about implementation and addressing modes:Group A Group B A.ArrayI Indirect AddressingB Relocatable codeII Indexed AddressingC Array as parameterIIIBase...
Bikram
451
views
Bikram
asked
Jan 16, 2017
GATE
tbb-mockgate-1
addressing-modes
co-and-architecture
+
–
0
votes
0
answers
130
addressing mode
vaishali jhalani
346
views
vaishali jhalani
asked
Jan 7, 2017
CO and Architecture
co-and-architecture
addressing-modes
+
–
1
votes
1
answer
131
Addressing Mode
S1 : Relative mode is the addressing mode which can be used to write code in which reallocation is done at run time. S2 : Indirect addressing through registers can be used to access global variables. Which of the following option is correct?
S1 : Relative mode is the addressing mode which can be used to write code in which reallocation is done at run time.S2 : Indirect addressing through registers can be used...
srestha
1.9k
views
srestha
asked
Jan 7, 2017
CO and Architecture
co-and-architecture
addressing-modes
+
–
12
votes
1
answer
132
GATE CSE 1988 | Question: 9iii
In the program scheme given below indicate the instructions containing any operand needing relocation for position independent behaviour. Justify your answer. ...
In the program scheme given below indicate the instructions containing any operand needing relocation for position independent behaviour. Justify your answer.$$\begin{arr...
go_editor
3.6k
views
go_editor
asked
Dec 19, 2016
CO and Architecture
gate1988
normal
descriptive
co-and-architecture
addressing-modes
+
–
1
votes
2
answers
133
MadeEasy Test Series: CO & Architecture - Addressing Modes
Q. Consider an instruction of indirect addressing mode. what is the number of memory refrence by the processor when instruction is a computation that require a single operand and when it is a branch Instruction respectivily ?/ Option A) 2 ,2 B) 3,3 C)3,2 D) 2,3
Q. Consider an instruction of indirect addressing mode. what is the number of memory refrence by the processor when instruction is a computation that require a single ...
Hradesh patel
3.4k
views
Hradesh patel
asked
Nov 27, 2016
CO and Architecture
made-easy-test-series
co-and-architecture
addressing-modes
+
–
29
votes
3
answers
134
GATE CSE 1989 | Question: 2-ii
Match the pairs in the following questions: ...
Match the pairs in the following questions:$$\begin{array}{ll|ll}\hline \text{(A)} & \text{Base addressing} & \text{(p)} & \text{Reentranecy} \\\hline \text{(B)} & \text...
makhdoom ghaya
5.9k
views
makhdoom ghaya
asked
Nov 27, 2016
CO and Architecture
gate1989
match-the-following
co-and-architecture
addressing-modes
easy
+
–
0
votes
1
answer
135
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 25
What is the addressing mode of the below mentioned instruction? $’\text{MUL } \ R1, \ \#2’$ Indirect Indexed Immediate Direct
What is the addressing mode of the below mentioned instruction?$’\text{MUL } \ R1, \ \#2’$ Indirect Indexed Immediate Direct
Bikram
240
views
Bikram
asked
Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
addressing-modes
+
–
3
votes
2
answers
136
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 15
An instruction is stored at location $300$ with its address field at location $301$. The address field has a value of $400$. A processor register $R1$ contains the number $200$. If relative-addressing mode is used by the instruction (with $R1$ as index register) then the effective address is _________.
An instruction is stored at location $300$ with its address field at location $301$. The address field has a value of $400$. A processor register $R1$ contains the number...
Bikram
1.1k
views
Bikram
asked
Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
numerical-answers
addressing-modes
+
–
1
votes
4
answers
137
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 5
Which of the following is displacement addressing mode? Relative Indexed Base Immediate
Which of the following is displacement addressing mode?RelativeIndexedBaseImmediate
Bikram
1.0k
views
Bikram
asked
Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
addressing-modes
easy
+
–
5
votes
1
answer
138
MadeEasy Test Series: CO & Architecture - Addressing Modes
Here we will consider memory as word addressable or byte addressable?
Here we will consider memory as word addressable or byte addressable?
vaishali jhalani
1.8k
views
vaishali jhalani
asked
Nov 23, 2016
CO and Architecture
made-easy-test-series
co-and-architecture
addressing-modes
+
–
45
votes
6
answers
139
GATE CSE 1987 | Question: 1-V
The most relevant addressing mode to write position-independent codes is: Direct mode Indirect mode Relative mode Indexed mode
The most relevant addressing mode to write position-independent codes is:Direct modeIndirect modeRelative modeIndexed mode
makhdoom ghaya
15.2k
views
makhdoom ghaya
asked
Nov 8, 2016
CO and Architecture
gate1987
co-and-architecture
addressing-modes
easy
+
–
7
votes
2
answers
140
Addressing mode
What is the number of instrunctions needed to add n numbers in one address mode and store the result in the memory, assuming each number is already loaded in register? (A) n (B) n+1 (C) n-1 (D) 2n
What is the number of instrunctions needed to add n numbers in one address mode and store the result in the memory, assuming each number is already loaded in register?(A)...
Rakesh K
2.4k
views
Rakesh K
asked
Oct 30, 2016
CO and Architecture
co-and-architecture
addressing-modes
instruction-format
+
–
3
votes
1
answer
141
made easy
consider an instruction of indirect addressing mode. what are the number of memory references by the processor when an instruction is a computation that requires a single operand and when it is a branch instruction respectively?? According to me, the answer should be ... and two memory references for operand fetch as it is indirect. But the solution says 3,2. can someone check??
consider an instruction of indirect addressing mode. what are the number of memory references by the processor when an instruction is a computation that requires a single...
sushmita
3.8k
views
sushmita
asked
Oct 25, 2016
CO and Architecture
co-and-architecture
addressing-modes
+
–
1
votes
2
answers
142
Online
Rahul Jain25
1.0k
views
Rahul Jain25
asked
Oct 2, 2016
CO and Architecture
co-and-architecture
addressing-modes
+
–
1
votes
2
answers
143
UGC NET CSE | August 2016 | Part 3 | Question: 5
In _____ addressing mode, the operands are stored in the memory. The address of the corresponding memory location is given in a register which is specified in the instruction. Register direct Register indirect Base indexed Displacement
In _____ addressing mode, the operands are stored in the memory. The address of the corresponding memory location is given in a register which is specified in the instruc...
makhdoom ghaya
1.9k
views
makhdoom ghaya
asked
Sep 30, 2016
CO and Architecture
ugcnetcse-aug2016-paper3
co-and-architecture
addressing-modes
+
–
1
votes
1
answer
144
Computer organisation
Add #45,R1 what does it do?? according to site it stores result in R1 but my question is according to format after operation field(which is ADD here) Designation comes and only in cae of Store designation comes at last!!
Add #45,R1 what does it do?? according to site it stores result in R1 but my question is according to format after operation field(which is ADD here) Designation comes ...
WawwButterfly
1.6k
views
WawwButterfly
asked
Sep 20, 2016
CO and Architecture
co-and-architecture
addressing-modes
+
–
2
votes
1
answer
145
UGC NET CSE | December 2010 | Part 2 | Question: 34
The register or main memory location which contains the effective address of the operand is known as Pointer Special location Indexed register None of the above
The register or main memory location which contains the effective address of the operand is known asPointerSpecial locationIndexed registerNone of the above
makhdoom ghaya
1.1k
views
makhdoom ghaya
asked
Sep 8, 2016
CO and Architecture
ugcnetcse-dec2010-paper2
co-and-architecture
addressing-modes
+
–
4
votes
1
answer
146
UGC NET CSE | December 2013 | Part 3 | Question: 49
Match the following: ... $\text{a-iii, b-iv, c-i, d-ii}$ $\text{a-iii, b-i, c-iv, d-ii}$
Match the following:$\begin{array}{} {} & {\textbf{List -I}} & {} & {\textbf{List-II}} \\ \text{a.} & \text{Indexed addressing} & \text{i.} & \text{is not used when ...
go_editor
1.9k
views
go_editor
asked
Jul 29, 2016
CO and Architecture
ugcnetcse-dec2013-paper3
co-and-architecture
addressing-modes
+
–
0
votes
1
answer
147
UGC NET CSE | September 2013 | Part 3 | Question: 33
The instruction : MOV CL, [BX] [DI] + 8 represents the ____ addressing mode Based Relative Based Indexed Indexed Relative Register Indexed
The instruction : MOV CL, [BX] [DI] + 8 represents the ____ addressing modeBased RelativeBased IndexedIndexed RelativeRegister Indexed
go_editor
2.5k
views
go_editor
asked
Jul 24, 2016
CO and Architecture
ugcnetcse-sep2013-paper3
co-and-architecture
assembly
addressing-modes
+
–
1
votes
1
answer
148
doubt regarding Addressing mode
Can someone explain this line in simple words. The addressing mode specifies a rule for interpreting or modifying the address field of the instruction before the operand is actually executed.
Can someone explain this line in simple words.The addressing mode specifies a rule for interpreting or modifying the address field of the instruction before the operand i...
Don't you worry
469
views
Don't you worry
asked
Jul 21, 2016
CO and Architecture
co-and-architecture
addressing-modes
+
–
4
votes
1
answer
149
UGC NET CSE | June 2013 | Part 3 | Question: 41
Which of the following is not an addressing mode? Register indirect Autoincrement Relative indexed Immediate operand
Which of the following is not an addressing mode?Register indirectAutoincrementRelative indexedImmediate operand
go_editor
2.8k
views
go_editor
asked
Jul 17, 2016
CO and Architecture
ugcnetcse-june2013-paper3
co-and-architecture
assembly
addressing-modes
+
–
4
votes
4
answers
150
UGC NET CSE | June 2016 | Part 3 | Question: 5
The ____ addressing mode is similar to register indirect addressing mode, except that an offset is added to the contents of the register. The offset and register are specified in the instruction. Base indexed Base indexed plus displacement Indexed Displacement
The ____ addressing mode is similar to register indirect addressing mode, except that an offset is added to the contents of the register. The offset and register are spec...
Sanjay Sharma
3.1k
views
Sanjay Sharma
asked
Jul 11, 2016
CO and Architecture
ugcnetcse-june2016-paper3
co-and-architecture
addressing-modes
+
–
Page:
« prev
1
2
3
4
5
6
next »
Email or Username
Show
Hide
Password
I forgot my password
Remember
Log in
Register