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Recent questions tagged made-easy-test-series

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MadeEasy Test Series: CO & Architecture - Pipelining
Assume that execution of 200 instructions on a 6 staged pipeline where the target address is available at 4th stage.Let X be the probability of an instruction not being branch. ... Which is not possible.Where am I going wrong ?? :
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MadeEasy Test Series: CO & Architecture - Cache Memory
[MADEEASY]Consider a cache as follows :- Direct Mapped - 16 words total cache size - 4 words cache block sizeA sequence of 9 memory reads is performed in order from ... - Hit (in block 3)Its giving (D) But answer is given as (C).
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MadeEasy Test Series: CO & Architecture - Cache Memory
Assume that 16 bit cache address memory with cache size 1024 bytes. Block size of cache memory is 8 bytes and tag size is 9 bits. What is the associativity of cache memory?I am getting 8-way but answer is given as 4.
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MadeEasy Test Series: Digital Logic - Digital Counter
The number of Clock pulses needed to change the contents of an 8-bit-up-counter from (10101011) to (00111010) is ______________
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MadeEasy Test Series: Digital Logic - Carry Generator
The number of AND gates are present inside a 5-bit carry look ahead generator circuit are ______.
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MadeEasy Test Series: Algorithms - Dynamic Programming
Given an array of n numbers, give an algorithm for finding a contiguous subsequence A(i) ...A(j) for which the sum of elements is maximum.Eg. [-2, 11, -4, 13, -5, 2] → 20If ... n)(c.) O(n3), O(n)(d.) O(n2), O(1)Given answer is option (b.)
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MadeEasy Test Series: Digital Logic - Digital Counter
A binary counter is being pulsed by a 256 KHz clock signal.The output frequency from the MSB flip-flop is 2 KHz. The MOD number is _______ .
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MadeEasy Test Series: Digital Logic - Circuit Output
Consider the logical circuit shown below:If initially ABC = 000 then after how many clock pulses the circuit will reach its initial stage?a) 5b) 6c) 7d) 8
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MadeEasy Test Series: Operating System - Memory Management
The available main memory for loading processes is 128 MB which is divided into fixed number of partitions each of size 16 MB. If the processes of ... . The percentage of the internal fragmentation is ____________ (upto two decimal places)
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MadeEasy Test Series: Operating System - Process Schedule
Consider four processes all are arriving at time zero, with total execution time of 20, 10, 10 and 20 unit respectively. Each process spends the first 20% of execution time ... ] (upto one decimal place)my ans is 16.5 but ans is given 24.5
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MadeEasy Test Series: CO & Architecture - Pipelining
An instruction pipeline consists of following 5 stages:IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MA = Memory Access and WB = ... required to execute the code, without operand forwarding over a bypass network?9101114
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MadeEasy Test Series: Set Theory & Algebra - Relations
Given relation is reflexive or not.I think it is reflexive. and equivalence relation.
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MadeEasy Test Series: Combinatory - Permutation And Combinations
5 member commities are to be formed out of 10 people. The names are written in chits of paper and put into 6 boxes. Atleast _______ chits go into the same box.
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Madeeasy
Which of the following is true?$f(n)=O\left(\left(f\left(n\right)\right)^{2}\right)$f(n)=O\left(g\left(n\right)\right)\Rightarrow 2^{f\left (n\right)}=O\left( ... Both (a) and (b)
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MadeEasy Test Series: Compiler Design - Parsing
Which is true?a) Recursive Decent Parsers may suffer from infinite loop.b) Every LR grammer is unambiguous.c) Both a & bd) None Doubt: RDP and LL(1) can go in ... . free grammer. So, how can it go to infinite loop. Answer given was (c).
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MadeEasy Test Series: Theory of Computation- Closure Property
Which of the following is false ?a. Union of two recursive languages is recursive b. Intersection of regular and recursive language is recursivec. Union ... each option..and also describe intersection of regular and recursive is recursive..
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symmetric and antisymmetric
from definitoin of antisymmetry if aRb and bRa is present then a=b.so b should be answer,though d is right,but b is more appropriate
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MadeEasy Test Series: Algorithms - Graph Algorithms
Which of the following statements is/are true?S1: Dijkstra's algorithm is not affected by negative edge weight cycles in the graph and gives correct shortest path.S2: Bellman ... a) Only S2b) Only S1c) Both S1 and S2d) Neither S1 and nor S2
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quadruple notation
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MadeEasy Test Series: Computer Networks: Network Communication
When a signal travels through a transmission medium, its power becomes $100$ times. Then there would be power (a) Gain of $100$ (b) Loss of $100$(c) Gain of $20$dB (d) Loss of $20$dB
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MadeEasy Test Series 2018: Programming & DS - Binary search Tree
When searching for the key value 50 in a binary search tree, node containing the key values 10, 30, 40, 70, 90, 120, 150, 175 are traversed, in any ... occur on the search path from the root to node containing the value 50 are ________.
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MadeEasy Test Series: Programming & DS - Linked Lists
Delete the duplicate nodeDelete the alternate duplicate nodeDelete the adjacent nodeNone of these
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Which of the following statements are correct?
Which of the following statements are correct?S1: Binary search on array take less time than binary search on linked list.S2: Merge sort on array has more space ... i assume here that array is sorted. Answer given as Both S1 and S2.
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MadeEasy Test Series 2018: Programming & DS - Binary Tree
Consider the below code which run on any tree.In-order traversalPost-order traversalPre-order traversalNone of these
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MadeEasy Test Series: CO & Architecture - Instruction Format
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MadeEasy Test Series: Theory of Computation- Decidabiliy
Let L be the language containing only the string S where S = 0 if you will never clear the gate. ... L′ is the Complement of language L)L is decidableL′ is decidableL and L′ both are decidableL is undecidable
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Let L ≤ ML′ denote that language L is mapping reducible (many to one reducible) to language L
Let L ≤ ML′ denote that language L is mapping reducible (many to one reducible) to language L′. Which one of the following is True?If ... ; is recursive.Could anyone please solve this and explain the this reducibility logic ?
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Computer Networks DRDO-2008
Two ground stations are connected by a 10Mbps satellite link. The altitude of the satellite is 36,000km and the speed of the signal is 3x108 m/sec. ... size and there are no errors during communcations.1.5 Kbytes3 Kbytes4.5 Kbytes6 Kbytes
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Computer Networks question JNUEE 2006
Sliding Window Protocol with Selective Reject/Repeat gives better performance than other protocols whena) buffer is sufficient and bandwidth is limitedb) buffer ... and bandwidth is limitedd) buffer is sufficient and bandwidth is sufficient
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