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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2024-1} & \textbf{2024-2} & \textbf{2023} &  \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 2&2&2& 3 &1&2&1&2&3
\\\hline\textbf{2 Marks Count} & 3&3&4& 2 &2&2&2&2.67&4
\\\hline\textbf{Total Marks} & 8&8&10& 7 &5&6&\bf{5}&\bf{7.33}&\bf{10}\\\hline
\end{array}}}$$

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MadeEasy Subject Test 2019: CO & Architecture - Cache Memory
how to approcach such questions please help with all the three statements.
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CO madeeasy 2019 Multi level cache
please explain how hit ratio of L2 is taken as 0.5? instead of 0.9 as 10 misses are mentionedis it like as 20 misses at levle 1 out of which only 10 missed at level 2, so 10 out of 20 (and not 100) hence 0.5?
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MadeEasy Test Series: CO & Architecture - Cache Memory
As write through strategy is mentioned shouldnt we take SIMUALTANEOUS access formula for both read as well as write?when we will use read as parallel access formula?
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CO cpu performance
Considers a 2 ns clock cycle processor which consumes 8 cycles for MR instruction and 4 cycles for ALU instruction .relative frequencies of these instructions ... units are modified to double the performance. What is the performance gain?
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237
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Floating point
What's the funda about de-normalization?Like when to apply, when not to? What do we exactly infer from 'number in the denormal form'?Ex: +6.25 stored as 0 ... *-23).Why don't we apply de-normalization to this case while reporting the range?
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Co control word
The control field of a microinstruction supports 2 groups of control signals in which G1 indicates none or one of a 256 control signals and G2 indicates atmost 6 ... the remaining. What is the size of the control field in the instruction?
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DRAM chip question
A 32-bit wide main memory unit with a capacity of 1 GB is built using 256M 4-bit DRAM chips. The number of rows of memory cells in ... the time available for performing the memory read/write operations in the main memory unit is______%
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#pipeline #datahazard
The first instruction is arithmetic nature while instruction is a branch which of the following can occur in pipeline implementation1) RAW2) WAR3) WAW4) RAR
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MADE EASY
Consider an array A[100] and each element occupies 4 word a 32-word cache is used and divided into an 8-word blockWhat is the hit ratio for for(i=0;i<100;i++) x=A[i]+100;No of time block 0 is modified.
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Doubt : Previous year
Question : https://gateoverflow.in/91103/me-flt-4-q-58 ( i couldn't understand the discussion so solved like this := )(Please check where i am doing wrong ) Approach ... how to use it ? means when to add cache time in it and when to not )
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Calculating average access time in multi level cache
$h_1→L1$ hit ratio $h_2→L2$ hit ratio$C_1→ L1$ access time$C_2→ $Miss penalty to transfer information from L2 to L1$M→$ Miss penalty to transfer information from ... 's equation. Or something more is going on here, which I am unaware of?
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SELF DOUBT S
https://gateoverflow.in/1252/gate2007-54IN THIS QUESTION ALLOPERANDS ARE IN MEMORY THEN SO WHY WE ARE ONLY MOVING a into REGISTER NOT MOVING b into register ?
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Calculating cache penalty
For a system with two levels of cache, define $T_{c1}$ first-level cache access time; $T_{c2}$ second-level cache access time; $T_m$ memory access ... hit ratio. Provide an equation for effective access time $T_a$ for a read operation.
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Direct Mapping and set associative Mapping
https://gateoverflow.in/1851/gate2006-74https://gateoverflow.in/43565/gate2006-75can someone check this questions ?i am not getting, how without help of ... how we select lines and their respective Tags without help of Multiplexer ?
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Self Doubt
Conflict misses and inference misses reduces can be reduced by doubling the associativity of cache design?True or False with some explanation
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https://gateoverflow.in/753/gate2001-12?show=279851#c279851
doubt in this gate question- https://gateoverflow.in/753/gate2001-12?show=279851#c279851In instruction I3 how is it getting the value of r2 which is computed ... value of updated register values of write back stage??please resolve my doubt.
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Set associative cache implementation
Given the following specifications for an external cache memory: four-way set associative; line size of two 16-bit words; able to accommodate a total of ... that issues 24-bit addresses. Show how cache interprets the processor's addresses.
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#CO #2-Level Memory Hierarchy
What should be the answer and explanation for this question?https://gateoverflow.in/?qa=blob&qa_blobid=12048400696649494741
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confusion
What is the difference between ‘performance gain’ and ‘speed up’?
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Refresh overhead
Explain the refresh overhead in dram?
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Register renamimg
Give an example where register renamimg helps in eliminating the hazards
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153
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SELF DOUBT
https://gateoverflow.in/61144/ugcnet-june2015-iii-5NOT GETTING AT LAST …….
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Testbook subject test
what is the meaning of assertion.I know PC requires 1 memory access but they said 2.
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Self Doubt
How to find the number of mux required in a k-way set associative cache?Please give the implementation of the same.
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Hard disk data transfer rate , data rate
In case of disk, while doing questions , we have to find the data transfer rate . We do by how much data can be read in 1 rotation depending ... particular section of data.What is difference between data transfer rate and data rate given?
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Cache organisation
Do we use multiplexer in direct mapped cache ?
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ace Q
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memory write
why data Bus is not involved in memory write operation??
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METest_COA
Consider professor vamshi writes a program given below and run on a system which has 2way set associative 16KB data cache with 32 bytes block where each word size ... Total misses=$1023+128=1151$Please let me know If I went somewhere wrong.
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