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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2024-1} & \textbf{2024-2} & \textbf{2023} &  \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 2&2&2& 3 &1&2&1&2&3
\\\hline\textbf{2 Marks Count} & 3&3&4& 2 &2&2&2&2.67&4
\\\hline\textbf{Total Marks} & 8&8&10& 7 &5&6&\bf{5}&\bf{7.33}&\bf{10}\\\hline
\end{array}}}$$

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Recent questions in CO and Architecture

1 votes
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3211
write through
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3212
Which devices should get higher priority in assigning interrupts?
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3220
Ace Test Series: Digital Logic - ROM
I am getting (C). But answer given is (B). Where I have gone wrong?
I am getting (C). But answer given is (B). Where I have gone wrong?
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1 answer
3222
Cpu operand fetch speed
How many cycles here indexed addressing mode will take?
How many cycles here indexed addressing mode will take?
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2 votes
4 answers
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A hard disk with transfer rate of 20 kbps is constantly transferring data to memory using DMA cycle stealing mode
A hard disk with transfer rate of 20 kbps is constantly transferring data to memory using DMA cycle stealing mode. The size of data transfer is 32 bytes. The processor ru...
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1 votes
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3224
Gate 2016 syllabus C.O. memory interface
Memory Interface topic has been removed. Can someone tell me what kind question will not be asked. or what not to do in this section?
Memory Interface topic has been removed. Can someone tell me what kind question will not be asked.or what not to do in this section?
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3225
Decoder
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1 answer
3229
pipeline cycles
I think they calculated whole things wrong.. with operand forwarding answer is 9,but they drew wrong diagram..and without answer will be 14.as we can use id stage under wb stage. so answer shoyld be 5. @arjun sir.
I think they calculated whole things wrong.. with operand forwarding answer is 9,but they drew wrong diagram..and without answer will be 14.as we can use id stage under w...
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0 votes
2 answers
3230
Computer Organization Question
A computer with 32-bit wide data bus uses 4 K x 8 static RAM memory chips. The smallest memory this computer can have is: (a) 32 kb (b) 16 kb (c) 8 kb (d) 24 kb
A computer with 32-bit wide data bus uses 4 K x 8 static RAM memory chips. The smallest memory this computer can have is:(a) 32 kb (b) 16 kb (c) 8 kb (d) 24 kb
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