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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Pipeline hazards, Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\scriptsize{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}& \textbf{2022} & \textbf{2021-1}&\textbf{2021-2}&\textbf{2020}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count} & 3 &1&2&3&2&2&2&0&1&1&0&1.7&3
\\\hline\textbf{2 Marks Count} & 2 &2&2&4&1&3&4&3&2&5&1&2.8&5
\\\hline\textbf{Total Marks} & 7 &5&6&11&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline
\end{array}}}$$

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Most answered questions in CO and Architecture

5 votes
3 answers
221
NIELIT 2017 OCT Scientific Assistant A (CS) - Section C: 2
Which of the following is not a form of main memory? Instruction cache Instruction register Instruction opcode Translation look-aside buffer
Which of the following is not a form of main memory?Instruction cacheInstruction registerInstruction opcodeTranslation look-aside buffer
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0 votes
3 answers
222
NIELIT 2017 OCT Scientific Assistant A (CS) - Section B: 25
A micro programmed control unit Is faster than a hardwired unit Facilitates easy implementation of a new instruction Is useful when small programs are to be run All of the above
A micro programmed control unitIs faster than a hardwired unitFacilitates easy implementation of a new instructionIs useful when small programs are to be runAll of the ab...
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1 votes
3 answers
223
NIELIT 2016 DEC Scientist B (IT) - Section B: 55
The example of implied addressing is Stack addressing Indirect addressing Immediate addressing None of the above
The example of implied addressing isStack addressingIndirect addressingImmediate addressingNone of the above
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0 votes
3 answers
226
NIELIT 2017 DEC Scientist B - Section B: 14
We have $10$-stage pipeline, where the branch target conditions are resolved at stage $5$. How many stalls are there for an incorrectly predicted branch? $5$ $6$ $7$ $4$
We have $10$-stage pipeline, where the branch target conditions are resolved at stage $5$. How many stalls are there for an incorrectly predicted branch?$5$$6$$7$$4$
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1 votes
3 answers
227
NIELIT 2017 DEC Scientist B - Section B: 28
A RAM chip has $7$ address lines, $8$ data lines and $2$ chips select lines. Then the number of memory locations is __________ $2^{12}$ $2^{10}$ $2^{19}$ $2^{13}$
A RAM chip has $7$ address lines, $8$ data lines and $2$ chips select lines. Then the number of memory locations is __________$2^{12}$$2^{10}$$2^{19}$$2^{13}$
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1 votes
3 answers
228
NIELIT 2017 DEC Scientist B - Section B: 40
Which of the following is/are not features of RISC processor? Large number of addressing modes. Uniform instruction set. (i) Only (ii) Only Both (i) and (ii) None of the options
Which of the following is/are not features of RISC processor?Large number of addressing modes.Uniform instruction set.(i) Only(ii) OnlyBoth (i) and (ii)None of the option...
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1 votes
3 answers
229
UGC NET CSE | January 2017 | Part 3 | Question: 1
Which of the following is an interrupt according to temporal relationship with system clock? Maskable interrupt Periodic interrupt Division by zero Synchronous interrupt
Which of the following is an interrupt according to temporal relationship with system clock?Maskable interruptPeriodic interruptDivision by zeroSynchronous interrupt
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0 votes
3 answers
230
UGC NET CSE | January 2017 | Part 3 | Question: 4
Match the following : ... $\text{a-iv, b-ii, c-i, d-iii}$ $\text{a-iv, b-iii, c-ii, d-i}$
Match the following :$\begin{array}{clcl} & {\textbf{Addressing Mode}} & {} & {\textbf{Location of operand}} \\ \text{a.} & \text{Implied} & \text{i.} & \text{Registe...
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0 votes
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231
UGC NET CSE | January 2017 | Part 3 | Question: 5
In $8085$ microprocessor, the digit $5$ indicates that the microprocessor needs $-5$ volts, $+5$ volts supply $+5$ volts supply only $-5$ volts supply only $5$ MHz clock
In $8085$ microprocessor, the digit $5$ indicates that the microprocessor needs$-5$ volts, $+5$ volts supply$+5$ volts supply only$-5$ volts supply only$5$ MHz clock
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0 votes
3 answers
232
UGC NET CSE | January 2017 | Part 3 | Question: 6
In $8085$, which of the following performs: load register pair immediate operation? LDAX rp LKLD addr LXI rp, data INX rp
In $8085$, which of the following performs: load register pair immediate operation?LDAX rpLKLD addrLXI rp, dataINX rp
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6 votes
3 answers
235
ISRO2020-46
A magnetic disk has $100$ cylinders, each with $10$ tracks of $10$ sectors. If each sector contains $128$ bytes, what is the maximum capacity of the disk in kilobytes? $1,280,000$ $1280$ $1250$ $128,000$
A magnetic disk has $100$ cylinders, each with $10$ tracks of $10$ sectors. If each sector contains $128$ bytes, what is the maximum capacity of the disk in kilobytes?$1,...
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2 votes
3 answers
236
ISRO2020-43
Which of the following is an efficient method of cache updating? Snoopy writes Write through Write within Buffered write
Which of the following is an efficient method of cache updating?Snoopy writesWrite throughWrite withinBuffered write
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3 votes
3 answers
238
UGC NET CSE | June 2019 | Part 2 | Question: 11
Which type of addressing mode, less number of memory references are required? Immediate Implied Register Indexed
Which type of addressing mode, less number of memory references are required?ImmediateImpliedRegisterIndexed
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2 votes
3 answers
239
Ace Test Series: CO & Architecture - Instruction Execution
CPU can leave current instruction execution, without completing it for : Service of interrupt DMA Both Neither
CPU can leave current instruction execution, without completing it for :Service of interruptDMABothNeither
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